MA31753 Datasheet, PDF (22/30 Pages) Dynex Semiconductor – DMA Controller (DMAC) For An MA31750 System

MA31753
No. Description
Min
1 RESETN setup to CLK falling
2 RESETN hold after CLK falling
3 RESETN pulse wdth
4 A[0:15] setup to CSN falling (DMA XIO)
5 A[0:15] hold after DSN rising (DMA XIO)
6 CSN setup to DSN falling (DMA XIO)
7 CSN hold after DSN rising (DMA XIO)
8 MION, OIN, RDWN setup to AS rising (DMA XIO)
9 MION, OIN, RDWN hold after AS falling (DMA XIO)
10 RDN falling to D[0:16] driven (XIO read)
11 RDN falling to D[0:16] valid (XIO read)
12 RDN rising to D[0:16] invalid (XIO read)
13 RDN rising to D[0:16] tri-state (XIO read)
14 D[0:16] setup to WRN rising (XIO write)
15 D[0:16] hold after WRN rising (XIO write)
16 CLK falling to RDYN valid (DMA XIO)
17 CSN rising to RDYN tri-state (DMA XIO)
18 CSN falling to RDYN driven (DMA XIO)
19 CLK rising to AS rising
20 CLK falling to AS falling
21 A[0:15], AS[0:3], PS[0:3], PB[0:3] valid to AS rising
22 A[0:15], AS[0:3], PS[0:3], PB[0:3] valid after AS falling
23 MION, OIN, RDWN valid to DSN falling
24 MION, OIN, RDWN valid after DSN rising
25 CLK falling to AKRDN, AKWRN valid
26 CLK falling to DACKN[0:3] falling
27 CLK falling to DACKN[0:3] rising
28 CLK falling to DMAKN valid
29 CLK falling to DONEN valid
30 CLK falling to DSN, RDN, WRN valid
31 CLK falling to GEOUTN valid
32 CLK falling to INTRN valid
33 INTRN pulse width
34 CLK falling to LOCKN falling
35 CLK falling to LOCKN rising
36 CLK falling to SEC/FIRSTN valid
37 CLK falling to REQN valid
38 DREQN[0:3] setup to CLK falling
39 DREQN[0:3] hold after CLK falling
40 EXADEN, MPROEN, PEN setup to AS falling
41 EXADEN, MPROEN, PEN hold after AS faling
42 GRANTN setup to CLK falling
43 GRANTN hold after CLK falling
44 GEINN setup to CLK falling
45 GEINN hold after CLK falling
46 RDYN setup to CLK falling
47 RDYN hold after CLK falling
48 REQINN setup to CLK falling
49 REQINN hold after CLK falling
50 CLK rising to busses, strobes and control signals (note 1) tri-state
51 CLK falling to busses, strobes and control signals (note 1) driven
52 D[0:16] setup to AKRDN rising
53 D[0:16] hold after AKRDN rising
54 D[0:16] valid after AKWRN falling
55 D[0:16] valid after AKWRN rising
56 DPARN setup to CLK falling
57 DPARN hold after CLK falling
58 DTON setup to CLK falling
59 DTON hold after CLK falling
60 DMAE setup to CLK falling
61 DMAE hold after CLK falling
Max Units
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
ns
ns
ns
ns
-
ns
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
ns
ns
-
ns
-
ns
ns
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
Mil-Std-883, Method 5005, Subgroups 9, 10, 11.
TL = Low CLK period (ns), TH = High CLK period (ns).
Test Conditions: Vdd = 5.0V ±10%, Temperature = -55^oC to 125^oC, Vil = 0.0V, Vih = Vdd.
Output loads: All test load 1 unless otherwise specified.
Output Threshold: 50% Vdd (Load 1), Vss+1V, Vdd-1V (Load 2).
Note 1: A[0:15], AS[0:3], PS[0:3], PB[0:3], MION, OIN, RDWN, DMAKN, AS, DSN, RDN, WRN, LOCKN
Figure 15: Timing Parameters
22/30