MA28139 Datasheet, PDF (9/34 Pages) Dynex Semiconductor – OBDH Bus Terminal

CLOCK DETECTOR OPERATION
The Clock Detector architecture is shown in Figure 9; a
separate channel is essentially provided for each of the
Nominal and Redundant Interrogation busses. Associated
waveforms are shown in Figure 10.
MA28139
Figure 9: Clock Detector Architecture
Each channel contains an Edge Detector and a 5-bit
Watchdog Counter which respond only to high-to-low
transitions on their respective Interrogation bus DS1n inputs. A
common Bus Usage Detection circuit is used to generate time-
out pulses (used for internal and external reset) and bus
selection signals from the results of the watchdogs.
The local oscillator input, LOSC, is divided and decoded to
generate an active low reset and an active high sample clock.
When applied to both input Edge Detectors, these signals
permit input high-to-low transitions to be detected for one
LOSC cycle in every two (between the reset ↓ and sample
clock ↑). Once such transitions have been detected by a
sample clock, the associated watchdog counter is reset. The
MSB of each watchdog counter is used as an indication of its
bus’s status - active or inactive. Should the watchdog counter
overflow (i.e. its MSB be set to 1), the associated bus will be
considered inactive.
The status of the Nominal and Redundant Interrogation
busses is used to determine internal bus selection for the
modulation of Response and Block Transfer data in the
device’s RT mode. If neither bus is considered active, the
TlMEOUTn pin will be held low and RT mode reception of all 3
busses will be inhibited. If one bus is considered active, RT
mode reception will occur on the same set of bus circuits
(redundancy) as the active Interrogation bus. If both busses
are considered active, RT mode reception from the Nominal
set of bus circuits will be performed. RT mode transmission will
always occur on the same set of bus circuits (redundancy) as
selected for reception unless the SIMUL pin is held high, in
which case transmission will occur simultaneously on both the
Nominal and Redundant busses.
Both watchdog counters are fully set at power up to mark
both busses as inactive - in this way, a missing LOSC input will
not cause inactive busses to be deemed active.
For a single detected input transition, 17.5 to 18.5 LOSC
cycles will elapse before the relevant bus is considered
inactive. If near-instantaneous Nominal-to-Redundant or Dual-
to-Redundant bus handover occurs, the change-over will be
delayed by 18 to 19 LOSC cycles, in order to preserve the
priority of the Nominal bus. If near-instantaneous Redundant-
to-Nominal or Redundant-to-Dual bus handover occurs, the
change-over will occur after 1.5 to 2.5 LOSC cycles since the
Nominal bus takes priority. In either of these cases, a 1 LOSC
cycle TlMEOUTn pulse is always generated to ensure that
internal reset occurs.
The frequency of the local oscillator may be varied to make
the nominal time-out period of 17.5 LOSC cycles correspond
to any desired number of (missing) bits on the Interrogation
bus. Variation of the duty cycle does not vary the time-out
period. After 16 LOSC cycles without detected input
transitions, the associated watchdog times-out and is detected
on the next LOSC ↑ edge; the generation of a TlMEOUTn
pulse and reset are then inevitable.
For proper Clock Detector operation, (at least) one high-to-
low input transition must be detected within a period of 16
LOSC cycles of the last such detection, but transitions made
during alternate LOSC cycles (the phase is difficult to predict)
will not be detected. Local oscillator clock signals which are
harmonically-related to the modulation clock by an integer ratio
are thus a cause for concern, although this problem is perhaps
only likely to occur in experimental set-ups.
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