MA28139 Datasheet, PDF (18/34 Pages) Dynex Semiconductor – OBDH Bus Terminal

MA28139
Bit Position
RIRSYNC
RIRCLK
RIRDATA
RIRVAL
IRCLK
TRCLK
CTCLK
CHADD(0:7)
MOANS
or MOAND
PC
ANCLK
SOC
SH
ANSIN
DATARRT
FNRRT
Note 1: For any acquisition command to be decoded, the evaluated Memory Load Address must be zero. An evaluated
Memory Load Address of non-zero does not imply data acquisition.
Note 2: The Memory Load Address which is evaluated for decoding and addressing usage may vary from 3 to 5 bits.
If (EXTMLA1 = 1) and (EXTMLA2 = 0), the Memory Load Address field is extended to 4 bits and bit 11 of the
Interrogation will be treated as MLA(1).
If (EXTMLA2 = 1), the Memory Load Address field is extended to 5 bits and bits 10 and 11of the Interrogation will
be treated as MLA(0:1).
Any Interrogation bits treated as Extended Memory Load Address bits will not be treated as Terminal Address
bits; this facility is intended for 2x or 4x size expansion provided that up to 4 consecutive Terminal Addresses can
be used.
Note 3: The 8-bit Analog Single-Ended and 8-bit Analog Double-Ended Acquisition command responses are always 13
bits in length; the Destination Address is simply copied from the Interrogation into the Response.
Figure 16: 8-Bit Analog Single-Ended and 8-Bit Analog Double-Ended (Serial) Acquisition Waveforms
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