MA28139 Datasheet, PDF (15/34 Pages) Dynex Semiconductor – OBDH Bus Terminal

MA28139
Bit Position
RIRSYNC
RIRCLK
RIRDATA
RIRVAL
IRCLK
TRCLK
CTCLK
MLADD(0:4)
MLDATA
DATARRT
ENRRT
1
2
Bit Position
RIRSYNC
RIRCLK
RIRDATA
RIRVAL
IRCLK
TRCLK
CTCLK
MLADD(0:4)
MLDATA
DATARRT
ENRRT
1 = BCP(4) or TA(0)
2 = TA(4:5) or MLA(0:1)
Note 1: One Memory Load command takes 2 Interrogations to complete. Consecutive Memory Load commands are hence not
possible and form a protocol violation. The second Memory Load command of such a sequence will be rejected.
Note 2: For a Memory Load command to be decoded, the evaluated Memory Load Address must be non-zero. An evaluated
Memory Load Address of zero implies data aquisition.
Note 3: The Memory Load Address which is evaluated for decoding and addressing usage may vary from 3 to 5 bits.
If (EXTMLA1 = 1) and (EXTMLA2 = 0), the Memory Load Address field is extended to 4 bits and bit 11of the
Interrogation will be treated as MLA(1).
If (EXTMLA2 = 1), the Memory Load Address field is extended to 5 bits and bits 10 and 11of the Interrogation will be
treated as MLA(0:1).
Any Interrogation bits treated as Extended Memory Load Address bits will not be treated as Terminal Address bits; this
facility is intended for 2x or 4x size expansion provided that up to 4 consecutive Terminal Addresses can be used.
Note 4: The Memory Load command response is always 13-zeros.
Figure 13: Memory Load Command Waveforms
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