MA28139 Datasheet, PDF (21/34 Pages) Dynex Semiconductor – OBDH Bus Terminal

MA28139
THE ESA ON-BOARD DATA HANDLING
(OBDH) BUS
The dual redundant OBDH bus is connected to the OBT
bus interface via an input descriminator and an output bridge
driver circuit. These convert between the bipolar LITTON code
and the standard CMOS inputs and outputs of the IC.
The OBDH bus is divided into three parts:
A. INTERROGATION BUS (I BUS)
This bus is used to transfer data from the CT to the
RTs, as commands of 32 bit words, each bit being modulated
according to the Litton scheme shown in Figure 18. Each
Interrogation (or command) “slot” comprises 3 Sync bits, 3 or 4
BroadCast Pulses, 5 or 6 Terminal Address bits, 4 Destination
Address bits, 16 Data bits and a Parity bit.
B. RESPONSE BUS (R BUS)
This bus is used to send data from the RTs to the CT, (can
be used by RTs to receive data). Each response word
comprises the 4 Destination Address bits sent in the
corresponding Interrogation, either 8 or 16 Data bits from the
user (8 bits unless a 16 bit acquisition was requested and 8
zeros if no response data is required) and a single Stop bit
(used to ensure data is fully clocked through bus modems and
0 by convention).
C. BLOCK TRANSFER BUS (BT BUS)
Used to transfer blocks of data between the CT and RTs, in
either direction, as a contiguous block or stream of data bits.
FASTER OBDH/DBI COMPATIBLE NETWORKS
With analog components the OBT can interface any
equipment to the specified ESA OBDH bus at the nominal data
rate of 0.5 Mbps. Contract 5352 proved that analog
components limit OBDH data rate to 2 Mbps maximum. But
OBTs work to over 5 Mbps (10MHz with 2 clocks/bit Litton
coded). OBTs may be directly networked via digital bus
drivers/receivers, (eliminating analog components) using
Litton coded 4 wire (R2/DS1 and R4/DS2) busses (see OBDH
application note 1). MSS made a 3 metre optical OBDH
network for the Pegasus ion source.
DBIs may be directly connected but will not be Litton coded
with Parity on every bit, or exhibit modulation and
demodulation delays.
high -
0v -
low -
high -
0v -
low -
high -
0v -
low -
logical
"1"
logical
"0"
high -
0v -
0v -
low -
invalid
logic
"1"
invalid
logic
"0"
invalid
logic
"1"
logical
"1"
Synchronisation Pattern
Figure 18: Litton Coded Data
invalid
logic
"0"
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