MA17501 Datasheet, PDF (6/35 Pages) Dynex Semiconductor – Radiation Hard MIL-STD-1750A Execution unit

MA17501
3.0 INTERFACE SIGNALS
All signals comply with the voltage levels of Table 1. ln
addition, each of these functions is provided with Electrostatic
Discharge (ESD) protection diodes. All unused inputs must be
held to their inactive state via a connection to VDD or GND. A
500-ohm pull-up at the OSC input pin is recommended to
damp line reflections.
Throughout this data sheet, active low signals are denoted
by either a bar over the signal name or by following the name
with an "N" suffix, e.g., HOLDN. Referenced signals that are
not found on the MA17501 are preceded by the originating
chip's functional acronym in parentheses, e.g., (lU)DMARN.
A description of each pin function, grouped according to
functional interface, follows. The function acronym is
presented first, followed by its definition, its type, and its
detailed description. Function type is either input, output, high
impedance (Hi-z), or a combination thereof. Timing
characteristics of each of the functions described is provided in
Section 5.0.
3.1 POWER INTERFACE
The power interface consists of one 5V VDD connection
and three common GND pins.
3.2 CLOCKS
The Execution Unit provides the synchronisation clocks for
the MAS281 chip set. Together these clocks form the basic
operation cycle.
3.2.1 Oscillator (OSC)
lnput. The MA17501 requires a single external oscillator
input for operation. The EU converts the oscillator into the five
other clocks listed in this section. To minimise skew between
OSC edges and signals derived from OSC, the OSC rise and
fall times should be minimised. lt is recommended that a clock
driver with high drive capability, such as a 54AS244,
54ALS244 or 54HST240, be used to drive the OSC input.
ln order to avoid double clocking due to line reflections, a
500-ohm pull-up resistor, placed close to the EU, is
recommended.
3.2.2 Synchronisation Clock (SYNCN)
Output. The MA17501 provides the MAS281
Synchronisation Clock output to synchronise external circuitry
to the MAS281 machine cycle. The high-to-low transition of
this signal indicates the start of a new machine cycle.
SYNCN cycles associated with external memory or l/O bus
transactions are a minimum of five OSC cycles in duration and
may be extended by inserting wait states via the RDYN input.
SYNCN low indicates that either an address or XlO command
is on the AD Bus; a high indicates data is on the bus. Wait
states extend the high state of SYNCN.
SYNCN cycles associated with internal CPU operations
are either five or six OSC cycles in duration. Six OSC cycles
are required for machine cycles associated with microcode
branches or with the execution of internally (Interrupt Unit)
decoded XlO commands. Five OSC cycles are used for all
other internal operations, e.g., register to register transfers,
ALU functions, etc.
[NOTE: For MAS281s operating at high OSC frequencies,
the lnterrupt Unit logic that creates lRDYN may cause a wait
state to be inserted during execution of internal XlO
commands. This would result in a SYNCN cycle of seven OSC
cycles duration. Though unlikely, this condition must be taken
into account in implementing a RDYN generation circuit. Refer
to the description of the RDYN signal for further details].
3.2.3 IU Synchronisation Clock (SYNCLKN)
Output. The SYNCLKN signal is a logical equivalent of the
SYNCN signal provided for Interrupt Unit synchronisation.
3.2.4 System Clock (SYSCLK1N)
Output. SYSCLK1N is the MA17501's synchronization
clock. It is the logical equivalent of SYNCN and SYNCLKN with
the exception that during PAUSEN low or during HLDAKN low,
SYSCLK1N is held in its low state. SYSCLK1N, like
SYNCLKN, has a VSS to VDD logic level swing.
3.2.5 Precharge Clock (CLKPCN)
Output. CLKPCN is used by the MA17502 Control Unit
(CU) to synchronize the precharging of the internal M Bus and
most other CU operations to the MAS281 machine cycle.
CLKPCN cycles associated with MAS281 external memory
or l/O bus transactions are a minimum of five OSC cycles in
duration and are extended when wait states are inserted via
the RDYN input. CLKPCN low indicates that the internal CU M
Bus is being precharged to the high state; the low-to-high
transition places the lower 20 bits of a microinstruction on the
external M Bus. Wait states extend the high state of CLKPCN.
When PAUSEN or HLDAKN is low, CLKPCN is held low.
CLKPCN cycles associated with internal MAS281
operations are either five or six OSC cycles in duration. Six
OSC cycles are required for machine cycles associated with
microcode branches or with the execution of internally
(lnterrupt Unit) decoded XlO commands. Five OSC cycles are
used for all other internal operations, e.g., register to register
transfers, ALU functions, etc.
[NOTE: For MAS281s operating at high OSC frequencies,
the lnterrupt Unit logic that creates lRDYN may cause a wait
state to be inserted during execution of internal XlO
commands. This would result in a CLKPCN cycle of seven
OSC cycles duration.]
6/35