MA17501 Datasheet, PDF (11/35 Pages) Dynex Semiconductor – Radiation Hard MIL-STD-1750A Execution unit

MA17501
BIT
Test Coverage
1
Mlcrocode Sequencer
IB Register Control
Barrel Shifter
Byte Operations and Flags
BIT Fail Codes (FT_13,14,15)
100
2
Temporary Registers (T0 - T7)
101
Microcode Flags
Multiply
Divide
3
Interrupt Unit - MK, Pl, FT
111
Enable/Disable Interrupts
4
Status Word Control
110
User Flags
General Registers (R0 - R15
5
Timer A
111
Timer B
-
BIT Pass/Fail Overhead
-
Note: BIT pass is indicated by all zeros in FT bits 13, 14, and 15.
Table 2: MAS281 BIT Summary
Cycles
221
166
214
154
763
26
4.2 INSTRUCTION EXECUTION
Instruction execution is characterised by a variety of
operations composed of various types of machine cycles. The
Execution Unit contains the clock generation circuitry that
creates the different machine cycles depending on the
particular operation being performed at the time. These
operations include: (1) internal CPU cycles, (2) instruction
fetches, (3) operand transfers, and (4) input/output transfers.
Instruction execution may be interrupted at the end of any
individual machine cycle by the PAUSEN (denoting DMA
operations) clock generation circuitry input, and at the
beginning of any given MIL-STD-1750A instruction by an
(IU)IRN or HOLDN low input to the Control Unit.
4.2.1 Internal CPU Cycles
All CPU data manipulation and housekeeping operations
are performed using internal CPU cycles. Internal CPU cycles
are either five or six OSC periods long and are characterised
by AS low and DSN, (IU)DDN, and M/ION high. Section 5.0
provides timing characteristics for internal CPU cycles.
The majority of lnternal CPU Cycles are five OSC period
machine cycles. Six OSC period machine cycles occur when
executing conditional jump or branch microinstructions; the EU
is calculating the branch condition to determine the state of the
T1 output signal.
4.2.2 Instruction Fetches
lnstruction fetches are used to keep the instruction pipeline
full. This ensures that the next instruction is ready for
execution when the preceding instruction is completed.
During jump and branch instruction execution the pipeline
is flushed, then refilled via two consecutive instruction fetches
starting at the new instruction location. The pipeline is also
refilled as part of the interrupt and Hold processing.
lnstruction fetches are five (minimum) OSC period
machine cycles characterised by IN/OPN, M/lON, and RD/WN
high. lnstruction fetches use pipeline registers lA and IB, the
instruction counter (lC), and the data input register (Dl).
Assuming an empty instruction pipeline (as a result of a reset,
jump or branch), the contents of lC are placed on the AD Bus
as an address. The returned value (the instruction) is stored in
the IA register. The lC register is incremented (dedicated
counter mode) and the next fetch is performed.
This second returned value, which may be an instruction or
an immediate operand, is stored in both the lA and Dl registers
as the previous contents of IA advance to the IB register to be
decoded into their microcoded routine. If the second returned
value is an immediate operand, a third instruction fetch will
occur with the instruction being loaded into lA only; Dl retains
the immediate operand.
The data portion (SYNCN high) of instruction fetch cycles
can be extended beyond their minimum five OSC periods by
use of the RDYN signal. RDYN held high during the high-to-
low transition of the machine cycles fifth OSC cycle will extend
the data portion of the machine cycle. The machine cycle can
be completed at any succeeding OSC cycle high-to-low
transition by enveloping this OSC edge with RDYN low.
4.2.3 Operand Transfers
Operand transfers are used to obtain operands to be used
by an instruction and to save any results of an instructions
execution. Machine cycles associated with operand transfers
are a minimum of five OSC periods in duration. The RDYN
signal can be used to insert wait states into the data portion of
the machine cycle (SYNCN high) to accommodate slow
memory.
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