MA17501 Datasheet, PDF (26/35 Pages) Dynex Semiconductor – Radiation Hard MIL-STD-1750A Execution unit

MA17501
No. Parameter
Test Conditions (1) (2)
Min (2) Typ (2) Max (2) Units
1
OSC ↑ to SYNCN
Load 1
2
OSC ↑ to SYSCLK1N
Load 1
3
OSC ↑ to SYNCLKN
Load 1
4
OSC ↑ to CLKPCN
Load 1
5
OSC ↑ to CLK02N
Load 1
6
SYNCN ↓ to AS ↑
Load 1
7
SYNCN ↓ to AS ↓ (4)
Load 1
8
SYNCN ↓ to DSN (Read)
Load 1
9
SYNCN ↓ to DSN ↓ (Read) (3)
Load 1
10
SYNCN ↓ to DSN ↓ (Write)
Load 1
11
SYNCN ↓ to DSN ↑ (Write) (3)
Load 1
12
SYNCN ↓ to Address Valid
Load 1
13
SYNCN ↓ to Data Valid
Load 1
14
SYNCN ↓ to M/ION, RD/WN, IN/OPN, INTREN Valid
Load 1
15
SYNCN ↓ to HLDAKN Valid
Load 1
16
SYSCLKN1 ↓ to T1 Valid
Load 1
17
SYSCLKN1 ↓ to OVIN Valid
Load 1
18
SYNCN ↓ to AD Bus Hi-Z (Read) (6)
Load 2
19
SYNCN ↓ to AD Bus Active (Read)
Load 2
20
PAUSEN ↓ to AD Bus Hi-Z (Read) (6)
Load 2
21
PAUSEN ↑ to AD Bus Valid
Load 2
22
PAUSEN ↓ to AS, DSN, M/ION, RD/WN, IN/IOPN Hi-Z (6) Load 2, 3
23
PAUSEN ↑ to AS, DSN, M/ION, RD/WN, IN/IOPN Valid Load 2, 3
24
HLDAKN ↓ to AD Bus Hi-Z (Read) (6)
Load 2
25
HLDAKN ↑ to AD Bus Valid
Load 2
26
HLDAKN ↓ to AS, DSN, M/ION, RD/WN, IN/IOPN Hi-Z (6) Load 2, 3
27
HLDAKN↑ to AS, DSN, M/ION, RD/WN, IN/IOPN Valid
Load 2, 3
28
Address after SYNCN ↓
Load 1
29
Data after SYNCN ↓
Load 1
30
M/ION, RD/WN, IN/OPN, INTREN after SYNCN
Load 1
31
HLDAKN after SYNCN ↓
Load 1
32
T1N after SYSCLK1N ↓
Load 1
33
OVIN after SYSCLK1N ↓
Load 1
34
Data to SYNCN ↓
35
Microcode to CLK02N ↓
36
Microcode to SYSCLK1N ↓
37
RDYN to OSC ↓
38
IRDYN to OSC ↓
39
Data after SYNCN ↓
40
Microcode after CLK02N ↓
41
Microcode after SYSCLK1N ↓
42
RDYN after OSC ↓
43
IRDYN after OSC ↓
44
SYNCN to SYNCN ↓ (7)
45
RESET ↑ to RESET ↓ (7)
46
RESET ↑ to Related Outputs Valid (7)
47
PIFN to Related Outputs Valid
48
HOLDN to Related Outputs Valid (7)
49
DSN to Data Valid (Write) (7)
Load 3 (DSN) Load 2 (Data)
50
SYNCN to SYNCLKN (No.1 - No.3)
51
CLKPCN to SYNCLKN (No.4 - No.3)
52
SYSCLK1 to CLKPC (No.2 - No.4)
10
1τ-10
2.5τ-10
3τ-5
10
3τ-5
4.5τ-5
15
3τ+15
12
5
-7
15
20
20
10
10
15
15
0
5
15
5
10
5τ-2
2
15
-5
-5
-5
40
ns
40
ns
40
ns
40
ns
40
ns
1τ+5
ns
2.5τ+15
ns
3τ+20
ns
30
ns
3τ+22
ns
4.5τ+10
ns
68
ns
3τ+45
ns
70
ns
20
ns
75
ns
100
ns
3τ+50
ns
ns
70
ns
60
ns
50
ns
59
ns
60
ns
50
ns
30
ns
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5τ+2
ns
ns
50
ns
50
ns
50
ns
ns
8
ns
5
ns
10
ns
MIL-STD-883, Method 5005, Subgroup 9, 10, 11
Notes: 1. T_A = +25°C, -55°C and +125°C tested at VDD = 4.5V and 5.5V
2. r = 1OSC period 0.5r implies 50% OSC duty cycle
3. Add 1r for internal XlO; nr for memory wait
4. Excluding DMA and Hold conditions
5. Unless otherwise noted: V_ll = ≥ 0.0V, V_IHTTL ≤ 4.0V, VIHOSC = 4.0V timing measured from 50% to 50% points
6. High impedance measured by 20% (of VDD) voltage change using 1K-ohm pullup resistor
7. Data obtained by characterisation or analysis, not routinely measured
8. Load 2 applies to bus interface signals AS, RD/W and IN/OP; Load 3 applies to bus interface signals M/ION and DSN
Table 4b: Timing Parameter Values
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