MA17501 Datasheet, PDF (2/35 Pages) Dynex Semiconductor – Radiation Hard MIL-STD-1750A Execution unit

MA17501
Figure 1: MAS281 Chip Set with Optional MA17504 and Support RAMs
As shown in Figure 1, the MAS281 is the minimum
processor configuration consisting of an Execution Unit, a
Control Unit, and an Interrupt Unit. This configuration is
capable of accessing a 64K-word address space. Addition of a
MA31751 allows access to a 1M-word address space and/or
provides hardware support for 1K-word memory block write
protection.
The EU, as with all components of the MAS281 chip set, is
fabricated with GEC Plessey Semiconductors CMOS/SOS
process technology. lnput and output buffers associated with
signals external to the MAS281 are TTL compatible.
Detailed descriptions of the EU's companion chips are
provided in separate data sheets. Additional discussions on
chip set system considerations, interconnection details, and
DAlS mix benchmarking analysis are provided in separate
applications notes.
The Execution Unit consists of a full function 16-bit ALU,
32-bit barrel shifter, 4 x 24-bit parallel multiplier, 24 x 16bit
dual-port RAM register file, processor status word register,
three operand transfer registers, three instruction fetch
registers, various interconnect buses, synchronization clock
generation logic, and microcode decode logic. Details of these
components are depicted in Figure 2 and are discussed below:
2.0 ARCHITECTURE
2.1 ALU
The ALU is a full function 16-bit arithmetic/logic unit
capable of performing arithmetic and logic operations on either
one or two 16-bit operands in a single machine cycle. ln
addition to operand manipulation, the ALU is used to compute
memory addresses.
The ALU supports 16-bit fixed-point single-precision, 32-bit
fixed-point double-precision, 32-bit floating-point, and 48-bit
floating-point extended-precision data in two’s complement
representation. Double-precision and extended-precision
operands are passed through the ALU 16 bits at a time on
consecutive machine cycles. Machine flags provide an
indication of ALU results and are used to set condition status
(CS) bits C, P, Z, and N in the Status Word Register. Condition
status bits and the Status Word register are discussed below.
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