MA17501 Datasheet, PDF (4/35 Pages) Dynex Semiconductor – Radiation Hard MIL-STD-1750A Execution unit

MA17501
Figure 2: MA17501 Execution Unit Architecture
2.5 STATUS WORD REGISTER
The Status Word Register (SW) holds the condition status
(CS) bits C, P, Z, and N generated by ALU operations. The SW
also stores the address state (AS) and processor state (PS)
fields. Figure 3 defines the Status Word Register storage
format. The CS bits are stored with each logical, shift, and
arithmetic operation performed by the ALU as required by MlL-
STD-1750A and remain valid until changed by subsequent
operations. The CS bits are interrogated during "jump on
condition" and "instruction counter relative" MlL-STD-1750A
branch instructions.
2.6 OPERAND TRANSFER REGISTERS
The Address (A), Data Output (DO), and Data lnput (Dl)
registers are referred to as Operand Transfer Registers. These
registers serve as storage buffers between internal EU buses
and the EU's externally accessible address/data (AD) Bus.
The DO register buffers data transferred from the EU to the AD
Bus. The A register buffers operand addresses and XlO
commands onto the AD Bus. The Dl register buffers data
transferred from the AD Bus to the EU .
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