MA17501 Datasheet, PDF (5/35 Pages) Dynex Semiconductor – Radiation Hard MIL-STD-1750A Execution unit

MA17501
A 20-bit multiplexed microcode (M) bus provides a
pathway between the Control Unit (CU) and the Execution
Register (E) buffered microcode decode logic on the EU chip.
Microcode placed on this bus by the CU controls all actions of
the EU.
Figure 3: Status Word Format
2.7 INSTRUCTION FETCH REGISTERS
The Instruction Counter (IC), Instruction A (IA), and
Instruction B (IB) registers allow sequential instruction fetches
to be performed without assistance from the ALU. The lC
register, which holds the 16-bit address of the next instruction
to be fetched from memory, is loaded automatically by reset,
jump, or branch operations. Once loaded, it functions as a
dedicated counter to sequence from one instruction to the
next. The current IC contents may be stored in registers R0
through R15 or in memory (pushed onto a stack) to provide
return linkages for subroutine calls. As part of the microcoded
interrupt handling routine the lC is saved in memory via the
interrupt linkage pointer.
Registers lA and IB provide an instruction look-ahead
capability. ln the case of 16-bit instructions, lB holds the
instruction currently executing while lA holds the next
instruction to be executed. ln the case of 32-bit instructions, IB
and lA each hold half of the instruction. IA and Dl (Dl stores the
immediate operands) are loaded as the instruction in lA is
transferred to lB for execution; if the instruction in lB uses an
immediate operand, lA is reloaded with the next instruction
while Dl maintains the immediate data. This overlapping of
operations allows higher performance levels to be achieved.
2.8 BUSES
Three 16-bit wide buses (R, S, and Y) interconnect the EU
data storage and computational elements. The R and S buses
accept operands from selected EU data storage elements and
route them to inputs of selected EU computational elements.
The Y, or destination, bus serves to route computational
results either back to EU data storage and computational
elements or to the various operand transfer registers.
A 16-bit multiplexed Address/Data (AD) Bus provides a
communications path between the EU, other components of
the MAS281 chip set, and any other devices mapped into the
chip set's address space. Data transfers between the AD Bus
and the R, S, and Y buses are buffered by the operand transfer
registers.
2.9 SYNCHRONISATION CLOCK GENERATION LOGIC
The Execution Unit generates all of the synchronisation
clocks required by the chip set and CPU system. The EU
converts an externally supplied oscillator signal into five
synchronisation signals: SYNCN, SYSCLK1N,SYNCLKN,
CLKPCN, CLK02N. The EU generates SYNCN for elements
external to the chip set whereas SYNCLKN and SYSCLK1N
are generated for the Interrupt Unit and internal EU
synchronisation, respectively. SYSCLK1N is also brought out
on a pin for use by external monitoring systems. The EU
generates CLKPCN and CLK02N for use in the Control Unit.
The CU uses CLKPCN to precharge the M Bus and transmit
the first microword while CLK02N is used to transmit
microword two.
The EU also contains the wait state generation interface.
Failure of memory or l/O subsystems to drive RDYN low at the
proper time during the DSN pulse causes the EU to hold
SYNCLKN, SYNCN, SYSCLK1N, and CLKPCN in the high
state; CLK02N, AS and DSN, in the low state; and RD/WN, IN/
OPN and M/ION in their current states for one or more
oscillator cycles beyond the end of the normal five OSC cycle
machine cycle. When RDYN is asserted low, the EU allows the
machine cycle to conclude at the high-to-low transition of the
current oscillator cycle. This will allow all the synchronisation
and control signals to resume normal operation.
Additionally, IRDYN is used to signal completion of internal
l/O command control of the lnterrupt Unit (IU). The IU thus can
extend the duration of the above mentioned bus signals.
Failure of the lU to drive lRDYN low at the proper time during
the DSN low pulse causes the EU to hold SYNCLKN, SYNCN,
SYSCLK1N, and CLKPCN in the high state; CLK02N, AS, and
DSN in the low state; and lN/OPN, M/lON, and RD/WN in the
state for the normal five OSC cycle machine cycle. When the
lU asserts IRDYN low, the EU allows the machine cycle to
conclude at the high-to-low transition of the current oscillator
cycle. This will allow all the synchronisation and control signals
to resume normal operation.
[NOTE: Whenever the EU is executing a machine cycle
which requires IRDYN to drop low for completion, the machine
cycle will be a minimum of six OSC cycles long. The maximum
duration of this machine cycle depends on the length of time
that the lU holds IRDYN high.]
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