DA14580 Datasheet, PDF (95/155 Pages) –

DA14580
Low Power Bluetooth Smart 4.2 SoC
FINAL
Table 123: UART2_HTX_REG (0x500011A4)
Bit
Mode Symbol
0
R/W UART_HALT_TX
Description
This register is use to halt transmissions for testing, so that
the transmit FIFO can be filled by the master when FIFOs
are implemented and enabled.
0 = Halt TX disabled
1 = Halt TX enabled
Note, if FIFOs are implemented and not enabled, the setting
of the halt TX register has no effect on operation.
Reset
0x0
Table 124: UART2_CPR_REG (0x500011F4)
Bit
Mode Symbol
15:0 R
CPR
Description
Component Parameter Register
Reset
0x0
Table 125: UART2_UCV_REG (0x500011F8)
Bit
Mode Symbol
15:0 R
UCV
Description
Component Version
Reset
0x33303
82A
Table 126: UART2_CTR_REG (0x500011FC)
Bit
Mode Symbol
15:0 R
CTR
Description
Component Type Register
Reset
0x44570
110
Table 127: SPI_CTRL_REG (0x50001200)
Bit
Mode Symbol
15
R/W SPI_EN_CTRL
14
R/W SPI_MINT
13
R
SPI_INT_BIT
12
R
SPI_DI
11
R
SPI_TXH
10
R/W SPI_FORCE_DO
9
R/W SPI_RST
8:7
R/W SPI_WORD
Description
0 = SPI_EN pin disabled in slave mode. Pin SPI_EN is don't
care.
1 = SPI_EN pin enabled in slave mode.
0 = Disable SPI_INT_BIT to the Interrupt Controller
1 = Enable SPI_INT_BIT to the Interrupt Controller
0 = RX Register or FIFO is empty.
1 = SPI interrupt. Data has been transmitted and received-
Must be reset by SW by writing to SPI_CLEAR_INT_REG.
Returns the actual value of pin SPI_DIN (delayed with two
internal SPI clock cycles)
0 = TX-FIFO is not full, data can be written.
1 = TX-FIFO is full, data can not be written.
0 = normal operation
1 = Force SPIDO output level to value of SPI_DO.
0 = normal operation
1 = Reset SPI. Same function as SPI_ON except that inter-
nal clock remain active.
00 = 8 bits mode, only SPI_RX_TX_REG0 used
01 = 16 bit mode, only SPI_RX_TX_REG0 used
10 = 32 bits mode, SPI_RX_TX_REG0 &
SPI_RX_TX_REG1 used
11 = 9 bits mode. Only valid in master mode.
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Datasheet
CFR0011-120-00-FM
Revision 3.3
95 of 155
08-Jun-2016
© 2014 Dialog Semiconductor