DA14580 Datasheet, PDF (28/155 Pages) –

DA14580
Low Power Bluetooth Smart 4.2 SoC
FINAL
Table 9: OTPC_AHBADR_REG (0x4000800C)
Bit
Mode Symbol
31:2 R/W OTPC_AHBADR
1:0
-
-
Description
Tthe AHB address used by the AHB master interface of the
controller (
bits [31:2]).
Reserved
Reset
0x0
0x0
Table 10: OTPC_CELADR_REG (0x40008010)
Bit
31:13
12:0
Mode
-
R/W
Symbol
-
OTPC_CELADR
Description
Reserved
Defines a word address inside the macrocell. Used in modes
AREAD and APROG and is automatically updated.
Reset
0x0
0x0
Table 11: OTPC_NWORDS_REG (0x40008014)
Bit
31:13
12:0
Mode
-
R/W
Symbol
-
OTPC_NWORDS
Description
Reserved
The number of words (minus one) for reading/programming
during the AREAD/APROG mode.
If in APROG mode, and the
OTPC_MODE_PRG_PORT_SEL is enabled (=1), this regis-
ter will not be used and will stay unchanged.
During mirroring, this register reflects the current amount of
data that will be copied. It keeps its value until be written by
the software with a new value. The number of the words that
remaining to be processed by the controller is contained in
the field OTPC_STAT_NWORDS.
Reset
0x0
0x0
Table 12: OTPC_FFPRT_REG (0x40008018)
Bit
Mode Symbol
31:0 R/W OTPC_FFPRT
Description
Provides access to the fifo through an access port. Write this
register with the corresponding data, when the APROG
mode is selected and the DMA is disabled. Read from this
register the corresponding data, when the AREAD mode is
selected and the DMA is disabled.
Check OTPC_STAT_FWORDS register for data/space avail-
ability, before accessing the fifo.
Reset
0x0
Table 13: OTPC_FFRD_REG (0x4000801C)
Bit
Mode Symbol
31:0 R
OTPC_FFRD
Description
Contains the value read from the fifo, after a read of the
OTPC_FFPRT_REG register.
Reset
0x0
Table 14: CLK_AMBA_REG (0x50000000)
Bit
Mode Symbol
15:8 -
-
7
R/W OTP_ENABLE
6
-
-
Description
Reserved
Clock enable for OTP controller
Reserved
Reset
0x0
0x0
0x0
Datasheet
CFR0011-120-00-FM
Revision 3.3
28 of 155
08-Jun-2016
© 2014 Dialog Semiconductor