DA14580 Datasheet, PDF (65/155 Pages) –

DA14580
Low Power Bluetooth Smart 4.2 SoC
FINAL
Table 80: UART_SFE_REG (0x50001098)
Bit
Mode Symbol
Description
0
R/W UART_SHADOW_FI Shadow FIFO Enable.
FO_ENABLE
This is a shadow register for the FIFO enable bit (FCR[0]).
This can be used to remove the burden of having to store the
previously written value to the FCR in memory and having to
mask this value so that only the FIFO enable bit gets
updated.This enables/disables the transmit (XMIT) and
receive (RCVR) FIFOs. If this bit is set to zero (disabled)
after being enabled then both the XMIT and RCVR controller
portion of FIFOs are reset.
Reset
0x0
Table 81: UART_SRT_REG (0x5000109C)
Bit
Mode Symbol
Description
15:2 -
-
Reserved
1:0
R/W UART_SHADOW_R Shadow RCVR Trigger.
CVR_TRIGGER
This is a shadow register for the RCVR trigger bits
(FCR[7:6]). This can be used to remove the burden of having
to store the previously written value to the FCR in memory
and having to mask this value so that only the RCVR trigger
bit gets updated.
This is used to select the trigger level in the receiver FIFO at
which the Received Data Available Interrupt is generated. It
also determines when the dma_rx_req_n signal is asserted
when DMA Mode (FCR[3]) = 1. The following trigger levels
are supported:
00 = 1 character in the FIFO
01 = FIFO ¼ full
10 = FIFO ½ full
11 = FIFO 2 less than full
Reset
0x0
0x0
Table 82: UART_STET_REG (0x500010A0)
Bit
Mode Symbol
Description
Reset
15:2 -
-
Reserved
0x0
1:0
R/W UART_SHADOW_TX Shadow TX Empty Trigger.
0x0
_EMPTY_TRIGGER This is a shadow register for the TX empty trigger bits
(FCR[5:4]). This can be used to remove the burden of having
to store the previously written value to the FCR in memory
and having to mask this value so that only the TX empty trig-
ger bit gets updated.
This is used to select the empty threshold level at which the
THRE Interrupts are generated when the mode is active.
The following trigger levels are supported:
00 = FIFO empty
01 = 2 characters in the FIFO
10 = FIFO ¼ full
11 = FIFO ½ full
Table 83: UART_HTX_REG (0x500010A4)
Bit
Mode Symbol
15:1 -
-
Description
Reserved
Reset
0x0
Datasheet
CFR0011-120-00-FM
Revision 3.3
65 of 155
08-Jun-2016
© 2014 Dialog Semiconductor