DA14580 Datasheet, PDF (1/155 Pages) –

DA14580
Low Power Bluetooth Smart 4.2 SoC
FINAL
General description
 84 kB ROM
The DA14580 integrated circuit has a fully integrated
radio transceiver and baseband processor for Blue-
tooth^® Smart. It can be used as a standalone applica-
tion processor or as a data pump in hosted systems.
 8 kB Retention SRAM
 Power management
 Integrated Buck/Boost DC-DC converter
 P0, P1, P2 and P3 ports with 3.3 V tolerance
 Easy decoupling of only 4 supply pins
The DA14580 supports a flexible memory architecture
 Supports coin (typ. 3.0 V) and alkaline (typ. 1.5 V)
for storing Bluetooth profiles and custom application
battery cells
code, which can be updated over the air (OTA). The
 10-bit ADC for battery voltage measurement
qualified Bluetooth Smart protocol stack is stored in a
dedicated ROM. All software runs on the ARM^® Cor-
tex^®-M0 processor via a simple scheduler.
 Digital controlled oscillators
 16 MHz crystal (±20 ppm max) and RC oscillator
 32 kHz crystal (±50 ppm, ±500 ppm max) and
The Bluetooth Smart firmware includes the L2CAP ser-
vice layer protocols, Security Manager (SM), Attribute
Protocol (ATT), the Generic Attribute Profile (GATT)
and the Generic Access Profile (GAP). All profiles pub-
lished by the Bluetooth SIG as well as custom profiles
are supported.
RCX oscillator
 General purpose, Capture and Sleep timers
 Digital interfaces
 General purpose I/Os: 14 (WLCSP34 package),
24 (QFN40 package), 32 (QFN48 package)
 2 UARTs with hardware flow control up to 1 MBd
 SPI+™ interface
The transceiver interfaces directly to the antenna and
 I2C bus at 100 kHz, 400 kHz
is fully compliant with the Bluetooth 4.2 standard.
 3-axes capable Quadrature Decoder
The DA14580 has dedicated hardware for the Link
Layer implementation of Bluetooth Smart and interface
controllers for enhanced connectivity capabilities.
 Analog interfaces
 4-channel 10-bit ADC
 Radio transceiver
 Fully integrated 2.4 GHz CMOS transceiver
Features
 Single wire antenna: no RF matching or RX/TX
switching required
 Complies with Bluetooth V4.2, ETSI EN 300 328 and
 Supply current at VBAT3V:
EN 300 440 Class 2 (Europe), FCC CFR47 Part 15
TX: 3.4 mA, RX: 3.7 mA (with ideal DC-DC)
(US) and ARIB STD-T66 (Japan)
 0 dBm transmit output power
 Processing power
 -20 dBm output power in “Near Field Mode”
 16 MHz 32 bit ARM Cortex-M0 with SWD inter-
 -93 dBm receiver sensitivity
face
 Packages:
 Dedicated Link Layer Processor
 WLCSP 34 pins, 2.436 mm x 2.436 mm
 AES-128 bit encryption Processor
 QFN 40 pins, 5 mm x 5 mm
 Memories
 QFN 48 pins, 6 mm x 6 mm
 32 kB One-Time-Programmable (OTP) memory
 KGD (wafer, dice)
 42 kB System SRAM
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System diagram
Datasheet
CFR0011-120-00-FM
Revision 3.3
1 of 155
08-Jun-2016
© 2014 Dialog Semiconductor