DS1780 Datasheet, PDF (6/28 Pages) Dallas Semiconductor – CPU Peripheral Monitor

2-WIRE SERIAL COMMUNICATION WITH THE DS1780 Figure 2
DS1780
OPERATION - Power-on
Applying power to the DS1780 causes a reset of several of the registers. Power-on conditions of the
registers are shown in Table 2 above. Some registers have indeterminate power-on values, such as the
Limit and RAM registers of the Value RAM page, and these are not shown in the table. Upon power-up
the ADC is inactive. Writing Limits into the Value RAM should usually be the first action performed
after power up. The RST pin is bi-directional. It forces RESET at power-on, but can also be pulled low to
force RESET internally.
OPERATION - Resets
The DS1780 features four distinct resetting functions. Each one has a different effect on register contents
and the state of the RST output following the event. Each one is explained below:
Power-on Reset - On POR, all internal logic is reset, and registers are cleared to their default state (see
tables 10.x). Because Value RAM is typically the first area programmed upon power-up, it does not have
a defined state upon POR. Also, on POR, the RST output will be pulled to an active low state for 20 ms
(minimum).
A POR occurs every time V_DD crosses the voltage level approximately equivalent to the sum of one n-
channel threshold (V_TN) and one p-channel threshold (V_TP), on a power-up or power-down condition.
DS1780 SRAM contents get “scrambled” when V_DD falls below the greater of one n-channel V_T or one p-
channel V_T. Therefore, SRAM contents will always be in a defined state as supply voltage reaches the
minimum spec level of 2.8V, even in a power supply brownout condition.
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