DS1780 Datasheet, PDF (13/28 Pages) Dallas Semiconductor – CPU Peripheral Monitor

DS1780
1. One-time Interrupt mode: Exceeding hot temperature limit causes an SMI that will remain active
indefinitely until reset by reading Interrupt Status Register 1 or cleared by the INT_Clear bit in the
Configuration register. Once an SMI event has occurred by crossing the hot temperature limit, then
subsequently reset, an SMI will not occur again until the temperature goes below hot temperature
hysteresis (low) limit.
2. Default Interrupt mode: Exceeding hot temperature limit causes an System Management Interrupt
(SMI) that will remain active indefinitely until reset by reading Interrupt Status Register 1 or cleared
by the INT_Clear bit in the Configuration Register. Once an Interrupt event has occurred by crossing
the Hot Temperature limit, then reset, an Interrupt will occur again once the next temperature
conversion has completed. The interrupts will continue to occur in this manner until the temperature
goes below the hot temperature hysteresis value.
3. Comparator mode: Exceeding hot temperature limit causes the SMI output to go active. SMI will
remain active until the temperature goes below the hot temperature limit. Once the temperature goes
below the hot temperature limit, SMI will become inactive. As in the default and one-time interrupt
modes, the SMI can also be cleared by reading Interrupt Status Register 1 or by setting the INT_Clear
bit in the configuration register.
Figure 4 below illustrates the three temperature interrupt modes.
Fan Speed Limits
The host programs 8-bit fan speed low limits for FAN1 and FAN2 inputs into Internal Address Registers
3Bh and 3Ch, respectively. Care must be taken to program the limit with respect to the divisor chosen for
each of the tachometer inputs. Refer to the “OPERATION - FAN Speed Data Format” section for details.
An interrupt will occur if measured fan speed falls below the programmed limit. Due to the nature of the
algorithm implemented, a count of 255 (max) represents a slow (or stopped) fan; i.e., tachometer counts
are inversely proportional to fan speed. Thus, the fan limit register will contain the maximum number of
counts (or the minimum fan speed) before which an interrupt will occur.
Chassis Intrusion Detection
The CHS input is an active high interrupt from any type of device that detects and captures chassis
intrusion violations. This could be accomplished mechanically, optically, or electrically, and circuitry
external to the DS1780 is expected to latch the event.
The design of the DS1780 allows this input to go high even with no power applied to the DS1780, and no
clamping or other interference with the line will occur. This line can also be pulled low for at least 20 ms
by the DS1780 to reset a typical Chassis Intrusion circuit. Accomplish this reset by setting Bit 6 of
Configuration Register high. The bit in the Register is self-clearing.
A possible chassis intrusion detector/latch is shown below in Figure 5.
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