DS1780 Datasheet, PDF (4/28 Pages) Dallas Semiconductor – CPU Peripheral Monitor

DS1780
A CHS (Chassis Intrusion) digital input is provided. The Chassis Intrusion input is designed to accept an
active high signal from an external circuit that latches when the case is removed from the computer; this
pin is a dual purpose pin which will be driven low by the DS1780 to reset the external circuit.
DS1780 FUNCTIONAL BLOCK DIAGRAM Figure 1
Note: R1 and R2 on the -12V resistance ladder should be ratioed such that approximately +2.5V appears
at the input pin (i.e., R1=4kΩ, R2=23.2 kΩ). If a second processor voltage needs to be monitored (V_CCP2),
leave R2 empty, and make R1 500Ω, with V_CCP2 appearing here.
2-WIRE SERIAL DATA BUS
When using the 2-wire bus, a write will always consist of the DS1780 2-wire slave address, followed by
the Internal Address Register byte, then the data byte. The Internal Address Register addresses are listed
below in Table 2. There are two cases for a read:
1. If the Internal Address Register is known to be at the desired Address, simply read the DS1780 with
the 2-wire slave address, followed by the data byte read from the DS1780.
2. If the Internal Address Register value is unknown, write to the DS1780 with the 2-wire slave address,
followed by the Internal Address Register byte. Then restart the Serial Communication with a Read
consisting of the 2-wire slave address, followed by the data byte read from the DS1780.
The default power-on 2-wire slave address for the DS1780 is 01011(A1)(A0) binary, where A0-A1
reflects the state of the pins defined by the same names. The address can be changed by writing any
desired value to the 2-wire Serial Address Register (excluding the 2 LSBs). This communication protocol
is depicted in the 2-wire timing diagrams of Figures 2 and 8.
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