DS1780 Datasheet, PDF (10/28 Pages) Dallas Semiconductor – CPU Peripheral Monitor

V_MIN (V_REF, R₁, R₂) ≅ -
R2
R1
V_REF
DS1780
V_MAX (V_REF,
R₁, R₂) ≅ V_REF-(V_REF-3.6)
é R1 + R2 ù
êë _R1 ú
If the +2.5V_S/+V_CCP2 is to be used to monitor a secondary processor core voltage (V_CCP2), R2 should be
removed and R1=500Ω. Table 6 below shows the voltage/data relationship for these inputs in the ideal
case. In this example, V_REF=+5.0V, R1=4.0 kΩ, and R2=23.2 kΩ.
Analog inputs will provide best accuracy when referred to the GNDA pin. A separate, low-impedance
ground plane for analog ground, which provides a ground point for the voltage dividers and analog
components will provide best performance but is not mandatory. Analog components such as voltage
dividers should be located physically as close as possible to the DS1780.
The power supply bypass, the parallel combination of 10 µF (electrolytic or tantalum) and 0.1 µF
(ceramic) bypass capacitors connected between pin 9 and ground, should also be located as close as
possible to the DS1780.
VOLTAGE/DATA RELATIONSHIPS FOR V_CCP VOLTAGE INPUTS
(+V_CCP1, +2.5VS/ +V_CCP2) Table 6
INPUT PIN
LSb WEIGHTING (mV)
+V_CCP1
14.1
+2.5V_S/+V_CCP2
96.0
(Used to monitor V_CCP)
(Used to monitor -12V)
ADC RESULT (BASE 10)
PIN VOLTAGE (V)
SUPPLY VOLTAGE (V)
0
0
-29.0
1
0.014
-28.90
2
0.028
-28.81
3
0.042
-28.71
4
0.056
-28.62
•
•
•
•
•
•
•
•
•
136
1.920
-15.94
137
1.934
-15.85
138
1.948
-15.75
139
1.962
-15.66
•
•
•
•
•
•
•
•
•
252
3.558
-4.808
253
3.572
-4.712
254
3.586
-4.616
255
3.60
-4.52
OPERATION - FAN Speed Data Format
Inputs are provided for signals from fans equipped with tachometer outputs. These are logic-level inputs
with an approximate threshold of 1.4V. Signal conditioning in the DS1780 accommodates the slow rise
and fall times typical of fan tachometer outputs. The maximum input signal range is 0 to V_DD. In the
event these inputs are supplied from fan outputs which exceed 0 to V_DD, either resistive division or diode
clamping must be included to keep inputs within an acceptable range, as shown in Figure 3. R2 is
selected so that it does not develop excessive voltage due to input leakage. R1 is selected based on R2 to
provide a minimum input of 2V and a maximum of V_DD. R1 should be as low as possible to provide the
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