DS1251Y Datasheet, PDF (4/12 Pages) Dallas Semiconductor – 4096K NV SRAM with Phantom Clock

DS1251Y
PHANTOM CLOCK REGISTER DEFINITION Figure 2
REGISTER
7
6
5
4
3
2
1
0
0
0.1 SEC
0.01 SEC
RANGE
(BCD)
00–99
1
0
10 SEC
SECONDS
00–59
2
0
10 MIN
MINUTES
3
12/24
0
10
HR
A/P
HOUR
4
0
0
OSC
RST
0
DAY
00–59
01–12
00–23
01–07
5
0
0
10 DATE
DATE
01–31
6
0
0
0
10
MONTH
MONTH
01–12
7
10 YEAR
YEAR
00–99
AM-PM/12/24 MODE
Bit 7 of the hours register is defined as the 12– or
24–hour mode select bit. When high, the 12–hour mode
is selected. In the 12–hour mode, bit 5 is the AM/PM bit
with logic high being PM. In the 24–hour mode, bit 5 is
the second 10-hour bit (20–23 hours).
OSCILLATOR AND RESET BITS
Bits 4 and 5 of the day register are used to control the
RESET and oscillator functions. Bit 4 controls the
RESET (pin 1). When the RESET bit is set to logic 1, the
RESET input pin is ignored. When the RESET bit is set
to logic 0, a low input on the RESET pin will cause the
Phantom Clock to abort data transfer without changing
data in the watch registers. Bit 5 controls the oscillator.
When set to logic 1, the oscillator is off. When set to log-
ic 0, the oscillator turns on and the watch becomes op-
erational. These bits are shipped from the factory set to
a logic 1.
ZERO BITS
Registers 1, 2, 3, 4, 5, and 6 contain one or more bits
which will always read logic 0. When writing these loca-
tions, either a logic 1 or 0 is acceptable.
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