DS1251Y Datasheet, PDF (3/12 Pages) Dallas Semiconductor – 4096K NV SRAM with Phantom Clock

DS1251Y
PHANTOM CLOCK
REGISTER INFORMATION
The Phantom Clock information is contained in eight
registers of 8–bits, each of which is sequentially ac-
cessed one bit at a time after the 64–bit pattern recogni-
tion sequence has been completed. When updating the
Phantom Clock registers, each register must be han-
dled in groups of 8–bits. Writing and reading individual
bits within a register could produce erroneous results.
These read/write registers are defined in Figure 2.
Data contained in the Phantom Clock register is in
binary coded decimal format (BCD). Reading and writ-
ing the registers is always accomplished by stepping
through all eight registers, starting with bit 0 of register 0
and ending with bit 7 of register 7.
PHANTOM CLOCK REGISTER DEFINITION Figure 1
BYTE 0
HEX
VALUE
7
6
5
4
3
2
1
0
1
1
0
0
0
1
0
1
C5
BYTE 1
0
0
1
1
1
0
1
0
3A
BYTE 2
1
0
1
0
0
0
1
1
A3
BYTE 3
0
1
0
1
1
1
0
0
5C
BYTE 4
1
1
0
0
0
1
0
1
C5
BYTE 5
0
0
1
1
1
0
1
0
3A
BYTE 6
1
0
1
0
0
0
1
1
A3
BYTE 7
0
1
0
1
1
1
0
0
5C
NOTE:
The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being accidentally dupli-
cated and causing inadvertent entry to the Phantom Clock is less than 1 in 10¹⁹. This pattern is sent to the Phantom
Clock LSB to MSB.
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