DS1251Y Datasheet, PDF (2/12 Pages) Dallas Semiconductor – 4096K NV SRAM with Phantom Clock

DS1251Y
RAM READ MODE
The DS1251Y executes a read cycle whenever WE
(Write Enable) is inactive (high) and CE (Chip Enable) is
active (low). The unique address specified by the 17 ad-
dress inputs (A0–A18) defines which of the 512K bytes
of data is to be accessed. Valid data will be available to
the eight data output drivers within t_ACC (Access Time)
after the last address input signal is stable, providing
that CE and OE (Output Enable) access times and
states are also satisfied. If OE and CE access times are
not satisfied, then data access must be measured from
the later occurring signal (CE or OE) and the limiting pa-
rameter is either t_CO for CE or t_OE for OE rather than ad-
dress access.
RAM WRITE MODE
The DS1251Y is in the write mode whenever the WE
and CE signals are in the active (low) state after address
inputs are stable. The latter occurring falling edge of CE
or WE will determine the start of the write cycle. The
write cycle is terminated by the earlier rising edge of CE
or WE. All address inputs must be kept valid throughout
the write cycle. WE must return to the high state for a
minimum recovery time (t_WR) before another cycle can
be initiated. The OE control signal should be kept inac-
tive (high) during write cycles to avoid bus contention.
However, if the output bus has been enabled (CE and
OE active) then WE will disable the outputs in t_ODW from
its falling edge.
DATA RETENTION MODE
The DS1251Y provides full functional capability for V_CC
greater than 4.5 volts and write protects by approxi-
mately 4.0 volts. Data is maintained in the absence of
V_CC without any additional support circuitry. The non-
volatile static RAM constantly monitors V_CC. Should the
supply voltage decay, the RAM automatically write pro-
tects itself. All inputs to the RAM become “don’t care”
and all outputs are high impedance. As V_CC falls below
approximately 3.0 volts, the power switching circuit con-
nects the lithium energy source to RAM to retain data.
During power–up, when V_CC rises above approximately
3.0 volts, the power switching circuit connects external
V_CC to the RAM and disconnects the lithium energy
source. Normal RAM operation can resume after V_CC
exceeds 4.5 volts.
PHANTOM CLOCK OPERATION
Communication with the Phantom Clock is established
by pattern recognition on a serial bit stream of 64 bits
which must be matched by executing 64 consecutive
write cycles containing the proper data on DQ0. All ac-
cesses which occur prior to recognition of the 64–bit pat-
tern are directed to memory.
After recognition is established, the next 64 read or write
cycles either extract or update data in the Phantom
Clock, and memory access is inhibited.
Data transfer to and from the timekeeping function is ac-
complished with a serial bit stream under control of Chip
Enable (CE), Output Enable (OE), and Write Enable
(WE). Initially, a read cycle to any memory location us-
ing the CE and OE control of the Phantom Clock starts
the pattern recognition sequence by moving a pointer to
the first bit of the 64–bit comparison register. Next, 64
consecutive write cycles are executed using the CE and
WE control of the SmartWatch. These 64 write cycles
are used only to gain access to the Phantom Clock.
Therefore, any address to the memory in the socket is
acceptable. However, the write cycles generated to
gain access to the Phantom Clock are also writing data
to a location in the mated RAM. The preferred way to
manage this requirement is to set aside just one ad-
dress location in RAM as a Phantom Clock scratch pad.
When the first write cycle is executed, it is compared to
bit 0 of the 64–bit comparison register. If a match is
found, the pointer increments to the next location of the
comparison register and awaits the next write cycle. If a
match is not found, the pointer does not advance and all
subsequent write cycles are ignored. If a read cycle oc-
curs at any time during pattern recognition, the present
sequence is aborted and the comparison register point-
er is reset. Pattern recognition continues for a total of 64
write cycles as described above until all the bits in the
comparison register have been matched (this bit pattern
is shown in Figure 1). With a correct match for 64–bits,
the Phantom Clock is enabled and data transfer to or
from the timekeeping registers can proceed. The next
64 cycles will cause the Phantom Clock to either receive
or transmit data on DQ0, depending on the level of the
OE pin or the WE pin. Cycles to other locations outside
the memory block can be interleaved with CE cycles
without interrupting the pattern recognition sequence or
data transfer sequence to the Phantom Clock.
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