W311_05 Datasheet, PDF (8/19 Pages) Cypress Semiconductor – FTG for VIA™ Pro-266 DDR Chipset

W311
Byte 9: System Reset and Watchdog Timer Register
Bit
Bit 7
Name
Reserved
Default
0
Reserved
Pin Description
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
PCI_DRV
Reserved
RST_EN_WD
RST_EN_FC
WD_TO_STATU
S
0
PCI clock output drive strength
0 = Normal
1 = High Drive
0
Reserved
0
This bit will enable the generation of a Reset pulse when a watchdog timer
time-out occurs.
0 = Disabled
1 = Enabled
0
This bit will enable the generation of a Reset pulse after a frequency change
occurs.
0 = Disabled
1 = Enabled
0
Watchdog Timer Time-out Status bit
0 = No time-out occurs (READ); Ignore (WRITE)
1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE)
Bit 1
WD_EN
Bit 0
Reserved
0
0 = Stop and re-load Watchdog Timer
1 = Enable Watchdog Timer. It will start counting down after a frequency
change occurs.
Note: W311 will generate system reset, reload a recovery frequency, and lock
itself into a recovery frequency mode after a watchdog timer time-out occurs.
Under recovery frequency mode, W311 will not respond to any attempt to
change output frequency via the SMBus control bytes. System software can
unlock W311 from its recovery frequency mode by clearing the WD_EN bit.
0
Reserved
Byte 10: Skew Control Register
Bit
Bit 7
Bit 6
Bit 5
Name
CPU_Skew2
CPU_Skew1
CPU_Skew0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
AGP_Skew1
AGP_Skew0
Default
0
0
0
0
0
0
0
0
CPU skew control
000 = Normal
001 = –150 ps
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
Reserved
Reserved
Reserved
AGP skew control
00 = Normal
01 = –150 ps
10 = +150 ps
11 = +300 ps
Description
Document #: 38-07703 Rev. **
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