W311_05 Datasheet, PDF (5/19 Pages) Cypress Semiconductor – FTG for VIA™ Pro-266 DDR Chipset

W311
W311 Serial Configuration Map
1. The serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
2. All unused register bits (reserved and N/A) should be
written to a “0” level.
3. All register bits labeled “Initialize to 0" must be written to
zero during initialization.
Byte 0: Control Register 0
Bit
Bit 7
Pin#
–
Name
Reserved
Default
0
Reserved
Description
Bit 6
Bit 5
Bit 4
–
SEL2
–
SEL1
–
SEL0
0
See Table 5
0
See Table 5
0
See Table 5
Bit 3
Bit 2
Bit 1
Bit 0
–
FS_Override
0
0 = Select operating frequency by FS[4:0] input pins
1 = Select operating frequency by SEL[4:0] settings
–
SEL4
1
See Table 5
–
SEL3
0
See Table 5
–
Reserved
0
Reserved
Byte 1: Control Register 1
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Pin#
-
-
-
-
Bit 3
35
Bit 2
38
Bit 1
39
Bit 0
42
Byte 2: Control Register 2
Bit
Bit 7
Pin#
20
Bit 6
18
Bit 5
17
Bit 4
16
Bit 3
14
Bit 2
13
Bit 1
11
Bit 0
10
Document #: 38-07703 Rev. **
Name
Reserved
Spread Select2
Spread Select1
Spread Select0
CPU3
CPU2
CPU1
APIC2
Default
0
0
0
0
1
1
1
1
Description
Reserved
‘000’ = Normal (spread off)
‘001’ = Test Mode
‘010’ = Reserved
‘011’ = Three-Stated
‘100’ = –0.5%
‘101’ = ± 0.5%
‘110’ = ± 0.25%
‘111’ = ± 0.38%
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Name
PC8
PCI7
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
Default
1
1
1
1
1
1
1
1
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Description
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