W311_05 Datasheet, PDF (6/19 Pages) Cypress Semiconductor – FTG for VIA™ Pro-266 DDR Chipset

W311
Byte 3: Control Register
Bit
Bit 7
Bit 6
Pin#
--
7
Bit 5
6
Bit 4
7
Bit 3
9
Bit 2
27
Bit 1
26
Bit 0
23
Name
Reserved
SEL_48MHz
48MHz
24_48MHz
PCI_F
AGP2
AGP1
AGP0
Default
0
0
1
1
1
1
1
1
Description
Reserved
0 = Select 24 MHz as output
1 = Select 48 MHz as output (default).
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Byte 4: Watchdog Timer Register
Bit
Bit 7
Pin#
-
Name
PCI_Skew1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
PCI_Skew0
-
WD_TIMER4
-
WD_TIMER3
-
WD_TIMER2
-
WD_TIMER1
-
WD_TIMER0
Default
0
0
1
1
1
1
1
Description
PCI skew control
00 = Normal
01 = –500 ps
10 = Reserved
11 = +500 ps
These bits store the time-out value of the Watchdog
Timer. The scale of the timer is determine by the pre
scaler.
The timer can support a value of 150 ms to 4.8 sec
when the pre-scalar is set to 150 ms. If the pre-scaler
is set to 2.5 sec, it can support a value from 2.5 sec
to 80 sec.
When the Watchdog Timer reaches to “0”, it will set
the WD_To_STATUS bit and generate Reset if
RST_EN_WD is enabled
0 = 150 ms
1 = 2.5 sec
Byte 5: Control Register 5
Bit
Bit 7
Bit 6
Pin#
6
7
Bit 5
44
Bit 4
45
Bit 3
-
Bit 2
-
Bit 1
47
Bit 0
48
Name
48Mhz_DRV
24_48MHz_DRV
APIC1
APIC0
Reserved
Reserved
REF1
REF0
Default
1
1
1
1
0
0
1
1
Description
0 = Norm, 1 = High Drive
0 = Norm, 1 = High Drive
(Active/Inactive)
(Active/Inactive)
Reserved
Reserved
(Active/Inactive)
(Active/Inactive)
Document #: 38-07703 Rev. **
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