W311_05 Datasheet, PDF (16/19 Pages) Cypress Semiconductor – FTG for VIA™ Pro-266 DDR Chipset

W311
PCI Clock Outputs (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
t_P
Period
Measured on rising edge at 1.5V
t_H
High Time
Duration of clock cycle above 2.4V
t_L
Low Time
Duration of clock cycle below 0.4V
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
t_F
Output Fall Edge Rate Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
t_JC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.
t_SK
Output Skew
Measured on rising edge at 1.5V
t_O
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
f_ST
Frequency Stabilization Assumes full supply voltage reached within 1 ms
from Power-up (cold
from power-up. Short cycles exist prior to frequency
start)
stabilization.
Z_o
AC Output Impedance Average value during switching transition. Used for
determining series termination value.
Min.
30
12
12
1
1
45
–
–
1.5
–
–
Typ.
–
–
–
–
–
–
–
–
–
–
30
Max.
–
–
–
4
4
55
500
500
4
3
–
Unit
ns
ns
ns
V/ns
V/ns
%
ps
ps
ns
ms
Ω
AGP Clock Outputs (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
t_P
Period
Measured on rising edge at 1.5V
t_H
High Time
Duration of clock cycle above 2.4V
t_L
Low Time
Duration of clock cycle below 0.4V
t_R
Output Rise Edge Rate
Measured from 0.4V to 2.4V
t_F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
t_JC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent
cycles.
t_SK
Output Skew
Measured on rising edge at 1.5V
f_ST
Frequency Stabilization from Assumes full supply voltage reached within
Power-up (cold start)
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Z_o
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Min.
15
5.25
5.05
1
1
45
–
–
–
–
APIC Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Frequency generated from PCI divided by 2
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
t_F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
f_ST
Frequency Stabilization Assumes full supply voltage reached within 1 ms
from Power-up (cold start) from power-up. Short cycles exist prior to
frequency stabilization.
Z_o
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Min.
0.5
0.5
45
Typ.
–
–
–
–
–
–
–
–
–
30
Typ.
PCI/2
40
Max.
–
–
–
4
4
55
500
Unit
ns
ns
ns
V/ns
V/ns
%
ps
250 ps
3 ms
–
Ω
Max.
2
2
55
3
Unit
MHz
V/ns
V/ns
%
ms
Ω
Document #: 38-07703 Rev. **
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