W311_05 Datasheet, PDF (17/19 Pages) Cypress Semiconductor – FTG for VIA™ Pro-266 DDR Chipset

W311
REF Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Frequency generated by crystal oscillator
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
t_F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
f_ST
Frequency Stabilization Assumes full supply voltage reached within 1 ms
from Power-up (cold start) from power-up. Short cycles exist prior to
frequency stabilization.
Z_o
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Min.
0.5
0.5
45
–
–
Typ.
14.318
–
–
–
–
40
Max.
2
2
55
3
–
Unit
MHz
V/ns
V/ns
%
ms
Ω
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
f_D
Deviation from 48 MHz
(48.008 – 48)/48
m/n
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
t_F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
f_ST
Frequency Stabilization Assumes full supply voltage reached within 1 ms
from Power-up (cold start) from power-up. Short cycles exist prior to
frequency stabilization.
Z_o
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Min.
0.5
0.5
45
–
–
Typ.
48.008
+167
57/17
–
–
–
–
40
Max.
2
2
55
3
–
Unit
MHz
ppm
V/ns
V/ns
%
ms
Ω
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
f_D
Deviation from 24 MHz
(24.004 – 24)/24
m/n
PLL Ratio
(14.31818 MHz x 57/34 = 24.004 MHz)
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
t_F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
f_ST
Frequency Stabilization Assumes full supply voltage reached within 1 ms
from Power-up (cold start) from power-up. Short cycles exist prior to
frequency stabilization.
Z_o
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Min.
0.5
0.5
45
–
–
Typ.
24.004
+167
57/34
–
–
–
–
40
Max.
2
2
55
3
–a
Unit
MHz
ppm
V/ns
V/ns
%
ms
Ω
Ordering Information
Ordering Code
Package Type
W311H
48-pin SSOP
W311HT
48-pin SSOP - Tape and Reel
Lead-free
CYW311OXC
48-pin SSOP
CYW311OXCT
48-pin SSOP - Tape and Reel
Product Flow
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Document #: 38-07703 Rev. **
Page 17 of 19