W311_05 Datasheet, PDF (15/19 Pages) Cypress Semiconductor – FTG for VIA™ Pro-266 DDR Chipset

DC Electrical Characteristics: T_A = 0°C to +70°C, V_DD = 3.3V±5% and 2.5V±5% (continued)
Parameter
Description
Test Condition
Min.
Typ.
Crystal Oscillator
V_TH
X1 Input Threshold Voltage^[5]
C_LOAD
Load Capacitance, Imposed on
External Crystal^[6]
C_IN,X1
X1 Input Capacitance^[7]
Pin Capacitance/Inductance
V_DD = 3.3V
Pin X2 unconnected
–
1.65
–
18
–
28
C_IN
C_OUT
L_IN
Input Pin Capacitance
Output Pin Capacitance
Input Pin Inductance
Except X1 and X2
–
–
–
–
–
–
W311
Max.
Unit
–
V
–
pF
–
pF
5
pF
6
pF
7
nH
AC Electrical Characteristics
T_A = 0°C to +70°C, V_DD = 3.3V±5%, V_DD = 2.5V±5%f_XTL = 14.31818 MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output; Spread Spectrum is disabled.
CPU Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter Description
Test Condition
/Comments
CPU = 66.6 MHz CPU = 100 MHz CPU = 133 MHz
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
t_P
Period
Measured on rising edge at 15 – 15.5 10
1.25
– 10.5 7.5 – 8.0 ns
t_H
High Time
Duration of clock cycle
5.2 – – 3.0 – – 1.87 – – ns
above 2.0V
t_L
Low Time
Duration of clock cycle
5.0 – – 2.8 – – 1.67 – – ns
below 0.4V
t_R
Output Rise Edge Measured from 0.4V to
1 – 4 1 – 4 1 – 4 V/ns
Rate
2.0V
t_F
Output Fall Edge Measured from 2.0V to
1 – 4 1 – 4 1 – 4 V/ns
Rate
0.4V
t_D
Duty Cycle
Measured on rising and 45 – 55 45 – 55 45 – 55 %
falling edge at 1.25V
t_JC
Jitter,
Measured on rising edge at – – 250 – – 250 – – 250 ps
Cycle-to-Cycle
1.25V. Maximum
difference of cycle time
between two adjacent
cycles.
t_SK
Output Skew
Measured on rising edge at – – 175 – – 175 – – 175 ps
1.25V
f_ST
Frequency
Assumes full supply
– – 3 – – 3 – – 3 ms
Stabilization from voltage reached within
Power-up (cold start) 1 ms from power-up. Short
cycles exist prior to
frequency stabilization.
Z_o
AC Output
Average value during
– 20 – – 20 – – 20 – Ω
Impedance
switching transition. Used
for determining series
termination value.
Notes:
5. X1 input threshold voltage (typical) is 3.3V/2
6. The W311 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF;
this includes typical stray capacitance of short PCB traces to crystal.
7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
Document #: 38-07703 Rev. **
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