BCM4356XKUBGT Datasheet, PDF (72/195 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac 2×2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1, FM Receiver, and Wireless Charging

BCM4356 Advance Data Sheet
WLAN Host Interfaces
Section 10: WLAN Host Interfaces
SDIO v3.0
All three package options of the BCM4356 WLAN section provide support for SDIO version 3.0, including the
new UHS-I modes:
• DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3V signaling).
• HS: High-speed up to 50 MHz (3.3V signaling).
• SDR12: SDR up to 25 MHz (1.8V signaling).
• SDR25: SDR up to 50 MHz (1.8V signaling).
• SDR50: SDR up to 100 MHz (1.8V signaling).
• SDR104: SDR up to 208 MHz (1.8V signaling)
• DDR50: DDR up to 50 MHz (1.8V signaling).
Note: The BCM4356 is backward compatible with SDIO v2.0 host interfaces.
The SDIO interface also has the ability to map the interrupt signal on to a GPIO pin for applications requiring an
interrupt different from the one provided by the SDIO interface. The ability to force control of the gated clocks
from within the device is also provided. SDIO mode is enabled by strapping options. Refer to Table 23 on
page 120 WLAN GPIO Functions and Strapping Options.
The following three functions are supported:
• Function 0 Standard SDIO function (max. BlockSize/ByteCount = 32B)
• Function 1 Backplane Function to access the internal system-on-chip (SoC) address space
(max. BlockSize/ByteCount = 64B)
• Function 2 WLAN Function for efficient WLAN packet transfer through DMA
(max. BlockSize/ByteCount = 512B)
SDIO Pins
DATA0
DATA1
DATA2
DATA3
CLK
CMD
Table 17: SDIO Pin Descriptions
SD 4-Bit Mode
Data line 0
Data line 1 or Interrupt
Data line 2 or Read Wait
Data line 3
Clock
Command line
DATA
IRQ
RW
N/C
CLK
CMD
SD 1-Bit Mode
Data line
Interrupt
Read Wait
Not used
Clock
Command line
Broadcom^®
May 8, 2015 • 4356-DS103-R
BROADCOM CONFIDENTIAL
Page 71