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BCM4356XKUBGT Datasheet, PDF (105/195 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac 2×2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1, FM Receiver, and Wireless Charging | |||
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BCM4356 Advance Data Sheet
Signal Descriptions
Table 21: WLCSP Signal Descriptions (Cont.)
Bump# Signal Name
RF Switch Control Lines
66
RF_SW_CTRL_0
175
RF_SW_CTRL_1
186
RF_SW_CTRL_2
193
RF_SW_CTRL_3
86
RF_SW_CTRL_4
183
RF_SW_CTRL_5
190
RF_SW_CTRL_6
197
RF_SW_CTRL_7
181
RF_SW_CTRL_8
187
RF_SW_CTRL_9
194
RF_SW_CTRL_10
202
RF_SW_CTRL_11
184
RF_SW_CTRL_12
191
RF_SW_CTRL_13
198
RF_SW_CTRL_14
207
RF_SW_CTRL_15
WLAN PCI Express Interface
174
PCIE_CLKREQ_L
180
PCIE_PERST_L
9
PCIE_RDN0
8
PCIE_RDP0
4
PCIE_REFCLKN
3
PCIE_REFCLKP
5
PCIE_TDN0
6
PCIE_TDP0
165
PCIE_PME_L
367
PCIE_TESTP
368
PCIE_TESTN
Type Description
O
Programmable RF switch control lines. The control
O
lines are programmable via the driver and NVRAM
file.
O
O
O
O
O
O
O
O
O
O
O
O
O
O
OD
I (PU)
I
I
I
I
O
O
OD
â
â
PCIe clock request signal which indicates when the
REFCLK to the PCIe interface can be gated.
1 = the clock can be gated
0 = the clock is required
PCIe System Reset. This input is the PCIe reset as
defined in the PCIe base specification version 1.1.
Receiver differential pair (Ã1 lane)
PCIE Differential Clock inputs (negative and positive).
100 MHz differential.
Transmitter differential pair (Ã1 lane)
PCI power management event output. Used to
request a change in the device or system power state.
The assertion and deassertion of this signal is
asynchronous to the PCIe reference clock. This signal
has an open-drain output structure, as per the PCI
Bus Local Bus Specification, revision 2.3.
PCIe test pin
Broadcom®
May 8, 2015 ⢠4356-DS103-R
BROADCOM CONFIDENTIAL
Page 104
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