BCM4356XKUBGT Datasheet, PDF (51/195 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac 2×2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1, FM Receiver, and Wireless Charging

BCM4356 Advance Data Sheet
PCM Interface
Long Frame Sync, Master Mode
Figure 15: PCM Timing Diagram (Long Frame Sync, Master Mode)
1
PCM_BCLK
2
3
4
PCM_SYNC
PCM_OUT
Bit 0
Bit 1
5
PCM_IN
Bit 0
Bit 1
8
HIGH IMPEDANCE
6
7
Table 9: PCM Interface Timing Specifications (Long Frame Sync, Master Mode)
Ref No.
1
2
3
4
5
6
7
8
Characteristics
PCM bit clock frequency
PCM bit clock LOW
PCM bit clock HIGH
PCM_SYNC delay
PCM_OUT delay
PCM_IN setup
PCM_IN hold
Delay from rising edge of PCM_BCLK during last bit
period to PCM_OUT becoming high impedance
Minimum
–
41
41
0
0
8
8
0
Typical
–
–
–
–
–
–
–
–
Maximum Unit
12
MHz
–
ns
–
ns
25
ns
25
ns
–
ns
–
ns
25
ns
Broadcom^®
May 8, 2015 • 4356-DS103-R
BROADCOM CONFIDENTIAL
Page 50