BCM4356XKUBGT Datasheet, PDF (114/195 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac 2×2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1, FM Receiver, and Wireless Charging

BCM4356 Advance Data Sheet
Signal Descriptions
Table 22: WLBGA Signal Descriptions (Cont.)
Ball# Signal Name
Type Description
WLAN PCI Express Interface
D5
PCIE_CLKREQ_L
C4
PCIE_PERST_L
B1
PCIE_RDN0
C1
PCIE_RDP0
A5
PCIE_REFCLKN
A4
PCIE_REFCLKP
A3
PCIE_TDN0
A2
PCIE_TDP0
C5
PCIE_PME_L
C3
PCIE_TESTP
C2
PCIE_TESTN
OD PCIe clock request signal which indicates when the
REFCLK to the PCIe interface can be gated.
1 = the clock can be gated
0 = the clock is required
I (PU) PCIe System Reset. This input is the PCIe reset as
defined in the PCIe base specification version 1.1.
I Receiver differential pair (×1 lane)
I
I PCIE Differential Clock inputs (negative and positive).
I ^{100 MHz differential.}
O Transmitter differential pair (×1 lane)
O
OD PCI power management event output. Used to
request a change in the device or system power state.
The assertion and deassertion of this signal is
asynchronous to the PCIe reference clock. This signal
has an open-drain output structure, as per the PCI
Bus Local Bus Specification, revision 2.3.
–
PCIe test pin
–
WLAN SDIO Bus Interface
Note: These signals can support alternate functionality depending on package and host interface mode. See
Table 26: “GPIO Alternative Signal Functions,” on page 121 for additional details.
A8
SDIO_CLK
A9
SDIO_CMD
B9
SDIO_DATA_0
C9
SDIO_DATA_1
B8
SDIO_DATA_2
C8
SDIO_DATA_3
I SDIO clock input
I/O SDIO command line
I/O SDIO data line 0
I/O SDIO data line 1
I/O SDIO data line 2
I/O SDIO data line 3
Broadcom^®
May 8, 2015 • 4356-DS103-R
BROADCOM CONFIDENTIAL
Page 113