BCM4356XKUBGT Datasheet, PDF (31/195 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac 2×2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1, FM Receiver, and Wireless Charging

BCM4356 Advance Data Sheet
External Frequency Reference
Table 3: Crystal Oscillator and External Clock—Requirements and Performance (Cont.)
Crystal^a
External Frequency
Reference^{b, c}
Parameter
Conditions/Notes
Min. Typ. Max. Min. Typ. Max. Units
Drive level
External crystal must be able to 200 –
–
–
–
tolerate this drive level.
– μW
Input impedance Resistive
(WRF_XTAL_IN) _Capacitive
–
–
– 30 100
– kΩ
–
– 7.5 –
–
7.5 pF
WRF_XTAL_IN
Input low level
DC-coupled digital signal
–
–
–
0
–
0.2 V
WRF_XTAL_IN
Input high level
DC-coupled digital signal
–
–
– 1.0 – 1.26 V
WRF_XTAL_IN
input voltage
(see Figure 8)
AC-coupled analog signal
–
–
– 400 –
1200 mV_p-p
Duty cycle
37.4 MHz clock
–
–
– 40 50
60 %
Phase Noise^g
37.4 MHz clock at 10 kHz offset –
–
–
–
– –129 dBc/Hz
(IEEE 802.11b/g) ^{37.4 MHz clock at 100 kHz offset –}
–
–
–
– –136 dBc/Hz
Phase Noise^g
37.4 MHz clock at 10 kHz offset –
–
–
–
– –137 dBc/Hz
(IEEE 802.11a) ^{37.4 MHz clock at 100 kHz offset –}
–
–
–
– –144 dBc/Hz
Phase Noise^g
37.4 MHz clock at 10 kHz offset –
–
–
–
– –134 dBc/Hz
(IEEE 802.11n, ^{37.4 MHz clock at 100 kHz offset –}
–
–
–
– –141 dBc/Hz
2.4 GHz)
Phase Noise^{g,h 37.4 MHz clock at 10 kHz offset –}
–
–
–
– –142 dBc/Hz
(IEEE 802.11n, ^{37.4 MHz clock at 100 kHz offset –}
–
–
–
– –149 dBc/Hz
5 GHz)
Phase Noise^g
37.4 MHz clock at 10 kHz offset –
–
–
–
– –150 dBc/Hz
(IEEE 802.11ac, ^{37.4 MHz clock at 100 kHz offset –}
–
–
–
– –157 dBc/Hz
5 GHz)
a. (Crystal) Use WRF_XTAL_IN and WRF_XTAL_OUT.
b. See “External Frequency Reference” on page 29 for alternate connection methods.
c. For a clock reference other than 37.4 MHz, 20 × log10(f/ 37.4) dB should be added to the limits, where f = the
reference clock frequency in MHz.
d. BT_TM6 should be tied low for a 52 MHz clock reference. For other frequencies, BT_TM6 should be tied high.
Note that 52 MHz is not an auto–detected frequency using the LPO clock.
e. The frequency step size is approximately 80 Hz resolution.
f. It is the responsibility of the equipment designer to select oscillator components that comply with these
specifications.
g. Assumes that external clock has a flat phase noise response above 100 kHz.
h. If the reference clock frequency is <35 MHz the phase noise requirements must be tightened by an additional
2 dB.
Broadcom^®
May 8, 2015 • 4356-DS103-R
BROADCOM CONFIDENTIAL
Page 30