5962-9061102XX Datasheet, PDF (7/15 Pages) Cypress Semiconductor – 32-Macrocell MAX® EPLD

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CY7C344
Typical Internal Switching Characteristics Over Operating Range^[7]
7C344-15 7C344-20 7C344-25
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
t_IN
Dedicated Input Pad and Buffer Delay
Com’l/Ind
4
5
7 ns
Mil
4
5
7
t_IO
I/O Input Pad and Buffer Delay
Com’l/Ind
4
5
7 ns
Mil
4
5
7
t_EXP
Expander Array Delay
Com’l/Ind
8
Mil
8
10
15 ns
10
15
t_LAD
Logic Array Data Delay
Com’l/Ind
7
Mil
7
9
10 ns
9
10
t_LAC
Logic Array Control Delay
Com’l/Ind
5
7
7 ns
Mil
5
7
7
t_OD
Output Buffer and Pad Delay
t_ZX
Output Buffer Enable Delay^[27]
Com’l/Ind
4
Mil
4
Com’l/Ind
7
Mil
7
5
5 ns
5
5
8
11 ns
8
11
t_XZ
Output Buffer Disable Delay
Com’l/Ind
7
Mil
7
8
11 ns
8
11
t_RSU
Register Set-Up Time Relative to Clock Signal Com’l/Ind 5
5
8
ns
at Register
Mil
5
5
8
t_RH
Register Hold Time Relative to Clock Signal at Com’l/Ind 7
Register
Mil
7
9
12
ns
9
12
t_LATCH
Flow-Through Latch Delay
Com’l/Ind
1
1
3 ns
Mil
1
1
3
t_RD
t_COMB
Register Delay
Transparent Mode Delay^[28]
Com’l/Ind
1
1
1 ns
Mil
1
1
1
Com’l/Ind
1
1
3 ns
Mil
1
1
3
t_CH
Clock HIGH Time
Com’l/Ind 6
7
8
ns
Mil
6
7
8
t_CL
Clock LOW Time
Com’l/Ind 6
7
8
ns
Mil
6
7
8
t_IC
Asynchronous Clock Logic Delay
Com’l/Ind
7
Mil
7
8
10 ns
8
10
t_ICS
Synchronous Clock Delay
Com’l/Ind
1
2
3 ns
Mil
1
2
3
t_FD
Feedback Delay
Com’l/Ind
1
1
1 ns
Mil
1
1
1
t_PRE
Asynchronous Register Preset Time
Com’l/Ind
5
6
9 ns
Mil
5
6
9
Notes:
27. Sample tested only for an output change of 500 mV.
28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial
operation.
Document #: 38-03006 Rev. *B
Page 7 of 15
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