5962-9061102XX Datasheet, PDF (3/15 Pages) Cypress Semiconductor – 32-Macrocell MAX® EPLD

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CY7C344
Timing Delays
Timing delays within the CY7C344 may be easily determined
using Warp^®, Warp Professional™, or Warp Enterprise™
software. The CY7C344 has fixed internal delays, allowing the
user to determine the worst case timing delays for any design.
Design Recommendations
Operation of the devices described herein with conditions
above those listed under “Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this data sheet is not implied. Exposure to absolute maximum
ratings conditions for extended periods of time may affect
device reliability. The CY7C344 contains circuitry to protect
device pins from high-static voltages or electric fields; however,
normal precautions should be taken to avoid applying any
voltage higher than maximum rated voltages.
For proper operation, input and output pins must be
constrained to the range GND ≤ (V_IN or V_OUT) ≤ V_CC. Unused
inputs must always be tied to an appropriate logic level (either V_CC or
GND). Each set of V_CC and GND pins must be connected together
directly at the device. Power supply decoupling capacitors of at least
0.2 µF must be connected between V_CC and GND. For the most
effective decoupling, each V_CC pin should be separately decoupled.
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum
expander delay t_EXP to the overall delay.
When calculating synchronous frequencies, use t_S1 if all inputs
are on the input pins. t_S2 should be used if data is applied at an I/O
pin. If t_S2 is greater than t_CO1, 1/t_S2 becomes the limiting frequency
in the data-path mode unless 1/(t_WH + t_WL) is less than 1/t_S2.
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t_EXP to t_S1. Determine which of
1/(t_WH + t_WL), 1/t_CO1, or 1/(t_EXP + t_S1) is the lowest frequency. The
lowest of these frequencies is the maximum data-path frequency for
the synchronous configuration.
When calculating external asynchronous frequencies, use
t_AS1 if all inputs are on dedicated input pins. If any data is applied to
an I/O pin, t_AS2 must be used as the required set-up time. If (t_AS2 +
t_AH) is greater than t_ACO1, 1/(t_AS2 + t_AH) becomes the limiting
frequency in the data-path mode unless 1/(t_AWH + t_AWL) is less than
1/(t_AS2 + t_AH).
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t_EXP to t_AS1. Determine which
of 1/(t_AWH + t_AWL), 1/t_ACO1, or 1/(t_EXP + t_AS1) is the lowest frequency.
The lowest of these frequencies is the maximum data-path frequency
for the asynchronous configuration.
The parameter t_OH indicates the system compatibility of this device
when driving other synchronous logic with positive input hold times,
which is controlled by the same synchronous clock. If t_OH is greater
than the minimum required input hold time of the subsequent
synchronous logic, then the devices are guaranteed to function
properly with a common synchronous clock under worst-case
environmental and supply voltage conditions.
The parameter t_AOH indicates the system compatibility of this
device when driving subsequent registered logic with a positive hold
time and using the same clock as the CY7C344. In general, if t_AOH
is greater than the minimum required input hold time of the subse-
quent logic (synchronous or asynchronous), then the devices are
guaranteed to function properly under worst-case environmental and
supply voltage conditions, provided the clock signal source is the
same. This also applies if expander logic is used in the clock signal
path of the driving device, but not for the driven device. This is due to
the expander logic in the second device’s clock signal path adding an
additional delay (t_EXP), causing the output data from the preceding
device to change prior to the arrival of the clock signal at the following
device’s register.
INPUT
INPUT
DELAY
t_IN
I/O
I/O
I/O DELAY
t_IO
EXPANDER
DELAY
t _EXP
LOGIC ARRAY
CONTROLDELAY t_CLR
t_LAC
t_PRE
LOGIC ARRAY t_RSU
DELAY
t_LAD
t_RH
REGISTER
t_RD
t_COMB
t_LATCH
SYSTEM CLOCK DELAYt_ICS
CLOCK
DELAY
t_IC
FEEDBACK
DELAY
t_FD
Figure 1. CY7C344 Timing Model
OUTPUT
DELAY
t_OD
t_XZ
t_ZX
OUTPUT
Document #: 38-03006 Rev. *B
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