5962-9061102XX Datasheet, PDF (4/15 Pages) Cypress Semiconductor – 32-Macrocell MAX® EPLD

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CY7C344
External Synchronous Switching Characteristics Over Operating Range ^[7]
7C344-15 7C344-20 7C344-25
Parameter
t_PD1
t_PD2
Description
Dedicated Input to Combinatorial Output Delay^[8]
I/O Input to Combinatorial Output Delay^[9]
Com’l/Ind
Mil
Com’l/Ind
Mil
Min. Max. Min. Max. Min. Max. Unit
15
20
25 ns
15
20
25
15
20
25 ns
15
20
25
t_PD3
Dedicated Input to Combinatorial Output Delay Com’l/Ind
with Expander Delay^[10]
Mil
30
30
30
30
40 ns
40
t_PD4
I/O Input to Combinatorial Output Delay with
Expander Delay^{[4, 11]}
Com’l/Ind
Mil
30
30
30
30
40 ns
40
t_EA
Input to Output Enable Delay^[4]
Com’l/Ind
20
20
25 ns
Mil
20
20
25
t_ER
Input to Output Disable Delay^[4]
Com’l/Ind
20
20
25 ns
Mil
20
20
25
t_CO1
Synchronous Clock Input to Output Delay
Com’l/Ind
10
12
15 ns
Mil
10
12
15
t_CO2
Synchronous Clock to Local Feedback to
Combinatorial Output^{[4, 12]}
Com’l/Ind
Mil
20
20
22
22
29 ns
29
t_S
Dedicated Input or Feedback Set-Up Time to Com’l/Ind 10
12
15
ns
Synchronous Clock Input
Mil
10
12
15
t_H
Input Hold Time from Synchronous Clock Input^[7] Com’l/Ind 0
0
0
ns
Mil
0
0
0
t_WH
Synchronous Clock Input HIGH Time^[4]
Com’l/Ind 6
7
8
ns
Mil
6
7
8
t_WL
Synchronous Clock Input LOW Time^[4]
Com’l/Ind 6
7
8
ns
Mil
6
7
8
t_RW
Asynchronous Clear Width^[4]
Com’l/Ind 20
20
25
ns
Mil
20
20
25
t_RR
Asynchronous Clear Recovery Time^[4]
Com’l/Ind 20
20
25
ns
Mil
20
20
25
t_RO
Asynchronous Clear to Registered Output
Delay^[4]
Com’l/Ind
Mil
15
15
20
20
25 ns
25
t_PW
Asynchronous Preset Width^[4]
Com’l /Ind 20
20
25
ns
Mil
20
20
25
t_PR
Asynchronous Preset Recovery Time^[4]
Com’l /Ind 20
20
25
ns
Mil
20
20
25
Notes:
8. This parameter is the delay from an input signal applied to a dedicated input pin to a combinatorial output on any output pin. This delay assumes no expander
terms are used to form the logic function.
9. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to
form the logic function.
10. This parameter is the delay associated with an input signal applied to a dedicated input pin to combinatorial output on any output pin. This delay assumes
expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter
is tested periodically by sampling production material.
11. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output pin. This delay assumes expander terms are used to
form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by
sampling production material.
12. This specification is a measure of the delay from synchronous register clock input to internal feedback of the register output signal to a combinatorial output for
which the registered output signal is used as an input. This parameter assumes no expanders are used in the logic of the combinatorial output and the register
is synchronously clocked. This parameter is tested periodically by sampling production material.
Document #: 38-03006 Rev. *B
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