5962-9061102XX Datasheet, PDF (10/15 Pages) Cypress Semiconductor – 32-Macrocell MAX® EPLD

USE ULTRA37000^TM FOR
ALL NEW DESIGNS
Switching Waveforms (continued)
Internal Asynchronous
t_AWH
t_AWL
t_IOt_R
t_F
CLOCK PIN
t_IN
CLOCK INTO
LOGIC ARRAY
CLOCK FROM
LOGIC ARRAY
DATA FROM
LOGIC ARRAY
REGISTER OUTPUT
TO LOCAL LAB
LOGIC ARRAY
REGISTER OUTPUT
TO ANOTHER LAB
t_IC
t_RSU
t_RH
t_RD,t_LATCH
t_FD
t_PIA
t_CLR,t_PRE
CY7C344
t_FD
Internal Synchronous (Input Path)
SYSTEM CLOCK PIN
t_CH
t_CL
SYSTEM CLOCK
AT REGISTER
DATA FROM
LOGIC ARRAY
t_IN
t_ICS
t_RSU
t_RH
Internal Synchronous (Output Path)
CLOCK FROM
LOGIC ARRAY
t_RD
t_OD
DATA FROM
LOGIC ARRAY
OUTPUT PIN
t_XZ
t_ZX
HIGH Z
Document #: 38-03006 Rev. *B
Page 10 of 15
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