5962-9061102XX Datasheet, PDF (5/15 Pages) Cypress Semiconductor – 32-Macrocell MAX® EPLD

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CY7C344
External Synchronous Switching Characteristics Over Operating Range (continued)^[7]
7C344-15 7C344-20 7C344-25
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
t_PO
t_CF
t_P
f_MAX1
Asynchronous Preset to Registered Output
Com’l /Ind
15
20
25 ns
Delay^[4]
Mil
15
20
25
Synchronous Clock to Local Feedback Input^{[4, 13]} Com’l /Ind
4
4
7 ns
Mil
4
4
7
External Synchronous Clock Period (1/f_MAX3)^[4] Com’l/Ind 13
14
16
ns
Mil
13
14
16
External Maximum Frequency(1/(t_CO1 + t_S))^{[4, 14]} Com’l/Ind 50.0
41.6
33.3
MHz
Mil
50.0
41.6
33.3
f_MAX2
Maximum Frequency with Internal Only
Feedback (1/(t_CF + t_S))^{[4, 15]}
Com’l/Ind 71.4
Mil
71.4
62.5
62.5
45.4
MHz
45.4
f_MAX3
Data Path Maximum Frequency, least of
1/(t_WL + t_WH), 1/(t_S + t_H), or (1/t_CO1)^{[4, 16]}
Com’l/Ind 83.3
Mil
83.3
71.4
71.4
62.5
MHz
62.5
f_MAX4
Maximum Register Toggle Frequency
1/(t_WL + t_WH)^{[4, 17]}
Com’l/Ind 83.3
71.4
62.5
MHz
Mil
83.3
71.4
62.5
t_OH
Output Data Stable Time from Synchronous
Clock Input^{[4, 18]}
Com’l/Ind 3
Mil
3
3
3
3
ns
3
Notes:
13. This specification is a measure of the delay associated with the internal register feedback path. This delay plus the register set-up time, t_S, is the minimum internal
period for an internal state machine configuration. This parameter is tested periodically by sampling production material.
14. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external only feedback can operate.
15. This specification indicates the guaranteed maximum frequency at which a state machine with internal-only feedback can operate. If register output states must
also control external points, this frequency can still be observed as long as it is less than 1/t_CO1. This specification assumes no expander logic is used. This parameter
is tested periodically by sampling production material.
16. This frequency indicates the maximum frequency at which the device may operate in data-path mode (dedicated input pin to output pin). This assumes that no
expander logic is used.
17. This specification indicates the guaranteed maximum frequency in synchronous mode, at which an individual output or buried register can be cycled by a clock
signal applied to either a dedicated input pin or an I/O pin.
18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.
Document #: 38-03006 Rev. *B
Page 5 of 15
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