PALC22V10D_07 Datasheet, PDF (6/12 Pages) Cypress Semiconductor – Flash Erasable, Reprogrammable CMOS PAL® Device

PALC22V10D
Commercial Switching Characteristics PALC22V10D^{[2, 7]}
22V10D-7
22V10D-10 22V10D-15 22V10D-25
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
t_PD
t_EA
t_ER
t_CO
t_S1
t_S2
t_H
t_P
t_WH
t_WL
f_MAX1
f_MAX2
f_MAX3
t_CF
Input to Output
Propagation Delay^{[8, 9]}
3
7.5
3
10
3
15
3
25
ns
Input to Output Enable Delay^[10]
8
10
15
25
ns
Input to Output Disable Delay^[11]
8
10
15
25
ns
Clock to Output Delay^{[8, 9]}
2
5
2
7
2
8
2
15
ns
Input or Feedback Set-Up Time
5
6
10
15
ns
Synchronous Preset Set-Up Time 6
7
10
15
ns
Input Hold Time
0
0
0
0
ns
External Clock Period (t_CO + t_S)
10
12
20
30
ns
Clock Width HIGH^[6]
3
3
6
13
ns
Clock Width LOW^[6]
3
3
6
13
ns
External Maximum Frequency
100
(1/(t_CO + t_S))^[12]
76.9
55.5
33.3
MHz
Data Path Maximum Frequency 166
142
83.3
35.7
MHz
(1/(t_WH + t_WL))^{[6, 13]}
Internal Feedback Maximum
133
111
68.9
38.5
MHz
Frequency (1/(t_CF + t_S))^[6,14]
Register Clock to
Feedback Input^{[6, 15]}
2.5
3
4.5
13
ns
t_AW
Asynchronous Reset Width
8
10
15
25
ns
t_AR
Asynchronous Reset Recovery
5
Time
6
10
25
ns
t_AP
Asynchronous Reset to
Registered Output Delay
12
13
20
25
ns
t_SPR
Synchronous Preset Recovery
6
Time
8
10
15
ns
t_PR
Power-Up Reset Time^[6,16]
1
1
1
1
µs
Notes:
7. Part (a) of AC Test Loads and Waveforms is used for all parameters except t_ER and t_EA(+). Part (b) of AC Test Loads and Waveforms is used for t_ER. Part (c) of AC Test
Loads and Waveforms is used for t_EA(+).
8. Min. times are tested initially and after any design or process changes that may affect these parameters.
9. This specification is guaranteed for all device outputs changing state in a given access cycle.
10. The test load of part (a) of AC Test Loads and Waveforms is used for measuring t_EA(-). The test load of part (c) of AC Test Loads and Waveforms is used for measuring
t_EA(+) only. Please see part (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels.
11. This parameter is measured as the time after output disable input that the previous output data state remains stable on the output. This delay is measured to
the point at which a previous HIGH level has fallen to 0.5 volts below V_OH min. or a previous LOW level has risen to 0.5 volts above V_OL max. Please see part (e) of AC
Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels.
12. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
13. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
14. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
15. This parameter is calculated from the clock period at f_MAX internal (1/f_MAX3) as measured (see Note above) minus t_S.
16. The registers in the PALC22V10D have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a
logic LOW state. The output state will depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure
proper operation, the rise in V_CC must be monotonic and the timing constraints depicted in Power-Up Reset Waveform must be satisfied.
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