PALC22V10D_07 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – Flash Erasable, Reprogrammable CMOS PAL® Device

1P AL C2 2V 10D
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For new designs, please refer to the PALCE22V10.
PALC22V10D
Flash Erasable, Reprogrammable CMOS PAL® Device
Features
• Advanced second-generation PAL architecture
• Low power
— 90 mA max. commercial (10 ns)
— 130 mA max. commercial (7.5 ns)
• CMOS Flash EPROM technology for electrical erasabil-
ity and reprogrammability
• Variable product terms
— 2 x(8 through 16) product terms
• User-programmable macrocell
— Output polarity control
— Individually selectable for registered or combinato-
rial operation
• Up to 22 input terms and 10 outputs
• DIP, LCC, and PLCC available
— 7.5 ns commercial version
5 ns t_CO
5 ns t_S
7.5 ns t_PD
133-MHz state machine
— 10 ns military and industrial versions
6 ns t_CO
6 ns t_S
10 ns t_PD
110-MHz state machine
— 15-ns commercial and military
versions
— 25-ns commercial and military
versions
• High reliability
— Proven Flash EPROM technology
100% programming and functional testing
Functional Description
The Cypress PALC22V10D is a CMOS Flash Erasable sec-
ond-generation programmable array logic device. It is imple-
mented with the familiar sum-of-products (AND-OR) logic
structure and the programmable macrocell.
The PALC22V10D is executed in a 24-pin 300-mil molded DIP,
a 300-mil cerDIP, a 28-lead square ceramic leadless chip car-
rier, a 28-lead square plastic leaded chip carrier, and provides
up to 22 inputs and 10 outputs. The 22V10D can be electrically
erased and reprogrammed. The programmable macrocell pro-
vides the capability of defining the architecture of each output
individually. Each of the 10 potential outputs may be specified
as “registered” or “combinatorial.” Polarity of each output may
also be individually selected, allowing complete flexibility of
output configuration. Further configurability is provided
through “array” configurable “output enable” for each potential
output. This feature allows the 10 outputs to be reconfigured
as inputs on an individual basis, or alternately used as a com-
bination I/O controlled by the programmable array.
PALC22V10D features a variable product term architecture.
There are 5 pairs of product term sums beginning at 8 product
terms per output and incrementing by 2 to 16 product terms
per output. By providing this variable structure, the PAL C
22V10D is optimized to the configurations found in a majority
of applications without creating devices that burden the prod-
uct term structures with unusable product terms and lower per-
formance.
Additional features of the Cypress PALC22V10D include a
synchronous preset and an asynchronous reset product term.
These product terms are common to all macrocells, eliminat-
ing the need to dedicate standard product terms for initializa-
tion functions. The device automatically resets upon pow-
er-up.
The PALC22V10D, featuring programmable macrocells and
variable product terms, provides a device with the flexibility to
implement logic functions in the 500- to 800-gate-array com-
plexity. Since each of the 10 output pins may be individually
configured as inputs on a temporary or permanent basis, func-
tions requiring up to 21 inputs and only a single output and
down to 12 inputs and 10 outputs are possible. The 10 poten-
tial outputs are enabled using product terms. Any output pin
may be permanently selected as an output or arbitrarily en-
abled as an output and an input through the selective use of
individual product terms associated with each output. Each of
these outputs is achieved through an individual programmable
macrocell. These macrocells are programmable to provide a
combinatorial or registered inverting or non-inverting output. In
a registered mode of operation, the output of the register is fed
back into the array, providing current status information to the
array. This information is available for establishing the next
result in applications such as control state machines. In a com-
binatorial configuration, the combinatorial output or, if the out-
put is disabled, the signal present on the I/O pin is made avail-
able to the array. The flexibility provided by both
programmable product term control of the outputs and variable
product terms allows a significant gain in functional density
through the use of programmable logic.
Along with this increase in functional density, the Cypress
PALC22V10D provides lower-power operation through the
use of CMOS technology, and increased testability with Flash
reprogrammability.
PAL is a registered trademark of Advanced Micro Devices
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 1991 – Revised October 1995