PALC22V10D_07 Datasheet, PDF (2/12 Pages) Cypress Semiconductor – Flash Erasable, Reprogrammable CMOS PAL® Device

PALC22V10D
Logic Block Diagram (PDIP/CDIP)
VSS
I
I
I
I
I
I
I
I
I
I
CP/I
12
11
10
9
8
7
6
5
4
3
2
1
PROGRAMMABLE
AND ARRAY
(132 X 44)
8
10
12
14
16
16
14
12
10
8
Reset
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Preset
13
14
15
16
17
18
19
I
I/O9
I/O8
I/O ₇
I/O6
I/O5
I/O4
Pin Configuration
LCC
Top View
20
21
22
I/O3
I/O2
I/O1
PLCC
Top View
23
24
I/O0
VCC
V10D–1
4 3 2 1 282726
I5
25 I/O ₂
I6
24 I/O ₃
I7
NC 8
23 I/O ₄
22 N/C
I9
21 I/O ₅
I 10
20 I/O ₆
I 11
19 I/O ₇
12131415161718
V10D–2
4 3 2 1 2827 26
I5
25 I/O ₂
I6
24 I/O ₃
I7
23 I/O ₄
NC 8
22 N/C
I9
I 10
21 I/O ₅
20 I/O ₆
I 11 _{121314 1516 1718} 19 I/O ₇
V10D–3
Configuration Table
Registered/Combinatorial
C₁
C₀
Configuration
0
0 Registered/Active LOW
0
1 Registered/Active HIGH
Configuration Table
Registered/Combinatorial
C₁
C₀
Configuration
1
0 Combinatorial/Active LOW
1
1 Combinatorial/Active HIGH
2