PSOC4000 Datasheet, PDF (5/34 Pages) Cypress Semiconductor – Programmable System-on-Chip

PSoC^® 4: PSoC 4000 Family
Datasheet
Functional Definition
CPU and Memory Subsystem
CPU
The Cortex-M0 CPU in the PSoC 4000 is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating. Most instructions are 16 bits in length and
the CPU executes a subset of the Thumb-2 instruction set. This
enables fully compatible, binary, upward migration of the code to
higher performance processors, such as the Cortex-M3 and M4.
It includes a nested vectored interrupt controller (NVIC) block
with eight interrupt inputs and also includes a Wakeup Interrupt
Controller (WIC). The WIC can wake the processor from the
Deep Sleep mode, allowing power to be switched off to the main
processor when the chip is in the Deep Sleep mode. The CPU
subsystem also includes a 24-bit timer called SYSTICK, which
can generate an interrupt.
The CPU also includes a debug interface, the serial wire debug
(SWD) interface, which is a 2-wire form of JTAG. The debug
configuration used for PSoC 4000 has four breakpoint (address)
comparators and two watchpoint (data) comparators.
Flash
The PSoC 4000 device has a flash module with a flash accel-
erator, tightly coupled to the CPU to improve average access
times from the flash block. The low-power flash block is designed
to deliver zero wait-state (WS) access time at 16 MHz.
SRAM
Two KB of SRAM are provided with zero wait-state access at
16 MHz.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
System Resources
Power System
The power system is described in detail in the section on Power
on page 12. It provides an assurance that voltage levels are as
required for each respective mode and either delays mode entry
(for example, on power-on reset (POR)) until voltage levels are
as required for proper functionality, or generates resets (for
example, on brown-out detection). The PSoC 4000 operates
with a single external supply over the range of either 1.8 V ±5%
(externally regulated) or 1.8 to 5.5 V (internally regulated) and
has three different power modes, transitions between which are
managed by the power system. The PSoC 4000 provides Active,
Sleep, and Deep Sleep low-power modes.
All subsystems are operational in Active mode. The CPU
subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep
mode, while all peripherals and interrupts are active with instan-
taneous wake-up on a wake-up event. In Deep Sleep mode, the
high-speed clock and associated circuitry is switched off;
wake-up from this mode takes 35 µS.
Clock System
The PSoC 4000 clock system is responsible for providing clocks
to all subsystems that require clocks and for switching between
different clock sources without glitching. In addition, the clock
system ensures that there are no metastable conditions.
The clock system for the PSoC 4000 consists of the internal main
oscillator (IMO) and the internal low-frequency oscillator (ILO)
and provision for an external clock.
Figure 3. PSoC 4000 MCU Clocking Architecture
IMO
External Clock
( connects to GPIO pin P 0.4 )
Divide By
2,4,8
FCPU
The F_CPU signal can be divided down to generate synchronous
clocks for the analog and digital peripherals. There are four clock
dividers for the PSoC 4000, each with 16-bit divide capability The
16-bit capability allows flexible generation of fine-grained
frequency values and is fully supported in PSoC Creator.
IMO Clock Source
The IMO is the primary source of internal clocking in the
PSoC 4000. It is trimmed during testing to achieve the specified
accuracy.The IMO default frequency is 24 MHz and it can be
adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO
tolerance with Cypress-provided calibration settings is ±2% (24
and 32 MHz).
ILO Clock Source
The ILO is a very low power, 40-kHz oscillator, which is primarily
used to generate clocks for the watchdog timer (WDT) and
peripheral operation in Deep Sleep mode. ILO-driven counters
can be calibrated to the IMO to improve accuracy.
Watchdog Timer
A watchdog timer is implemented in the clock block running from
the ILO; this allows watchdog operation during Deep Sleep and
generates a watchdog reset if not serviced before the set timeout
occurs. The watchdog reset is recorded in a Reset Cause
register, which is firmware readable.
Reset
The PSoC 4000 can be reset from a variety of sources including
a software reset. Reset events are asynchronous and guarantee
reversion to a known state. The reset cause is recorded in a
register, which is sticky through reset and allows software to
determine the cause of the reset. An XRES pin is reserved for
external reset on the 24-pin package. An internal POR is
provided on the 16-pin and 8-pin packages. The XRES pin has
an internal pull-up resistor that is always enabled. Reset is Active
Low.
Voltage Reference
The PSoC 4000 reference system generates all internally
required references. A 1.2-V voltage reference is provided for the
comparator. The IDACs are based on a ±5% reference.
Document Number: 001-89638 Rev. *E
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