PSOC4000 Datasheet, PDF (12/34 Pages) Cypress Semiconductor – Programmable System-on-Chip

PSoC^® 4: PSoC 4000 Family
Datasheet
Power
The following power system diagrams (Figure 9 and Figure 10)
show the set of power supply pins as implemented for the
PSoC 4000. The system has one regulator in Active mode for the
digital circuitry. There is no analog regulator; the analog circuits
run directly from the V_DD input. There is a separate regulator for
the Deep Sleep mode. The supply voltage range is either 1.8 V
±5% (externally regulated) or 1.8 V to 5.5 V (unregulated exter-
nally; regulated internally) with all functions and circuits
operating over that range.
The V_DDIO pin, available in the 16-pin QFN package, provides a
separate voltage domain for the following pins: P3.0, P3.1, and
P3.2. P3.0 and P3.1 can be I²C pins and the chip can thus
communicate with an I²C system, running at a different voltage
(where V_DDIO  V_DD). For example, V_DD can be 3.3 V and V_DDIO
can be 1.8 V.
The PSoC 4000 family allows two distinct modes of power supply
operation: Unregulated External Supply and Regulated External
Supply.
Unregulated External Supply
In this mode, the PSoC 4000 is powered by an external power
supply that can be anywhere in the range of 1.8 to 5.5 V. This
range is also designed for battery-powered operation. For
example, the chip can be powered from a battery system that
starts at 3.5 V and works down to 1.8 V. In this mode, the internal
regulator of the PSoC 4000 supplies the internal logic and the
V_CCD output of the PSoC 4000 must be bypassed to ground via
an external capacitor (0.1 µF; X5R ceramic or better).
Bypass capacitors must be used from V_DD to ground. The typical
practice for systems in this frequency range is to use a capacitor
in the 1-µF range, in parallel with a smaller capacitor (0.1 µF, for
example). Note that these are simply rules of thumb and that, for
critical applications, the PCB layout, lead inductance, and the
bypass capacitor parasitic should be simulated to design and
obtain optimal bypassing.
An example of a bypass scheme follows (V_DDIO is available on
the 16-QFN package).
Figure 9. 16-pin QFN Bypass Scheme Example - Unregulated
External Supply
Power supply connections when 1.8  V_DD  5. 5 V
1.8 V to 5.5 V
1 F
0. 1F
V_DD ^{PSoC 4000}
0. 1 F
V_CCD
1.71 V < V_DDIO  V_DD
0.1  F
V_DDIO
V_SS
Regulated External Supply
In this mode, the PSoC 4000 is powered by an external power
supply that must be within the range of 1.71 to 1.89 V; note that
this range needs to include the power supply ripple too. In this
mode, the V_DD and V_CCD pins are shorted together and
bypassed. The internal regulator should be disabled in the
firmware. Note that in this mode VDD (VCCD) should never
exceed 1.89 in any condition, including flash programming.
An example of a bypass scheme follows (V_DDIO is available on
the 16-QFN package).
Figure 10. 16-pin QFN Bypass Scheme Example - Regulated
External Supply
Power supply connections when 1.71  V_DD  1.89 V
1.71 V to 1.89 V
PSoC 4000
V_DD
1 F
0.1 F
V_CCD
1.71 V < VDDIO < VDD
0.1 F
V_DDIO
V_SS
Document Number: 001-89638 Rev. *E
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