BCM43903 Datasheet, PDF (49/87 Pages) Cypress Semiconductor – WICED™ IEEE 802.11 b/g/n SoC with an Embedded Applications Processor

BCM43903 Preliminary Data Sheet
Signal Descriptions
Table 7: Signal Descriptions (Cont.)
Ball Number Signal Name
SPI Interface
Type Description
Note: The SPI interface can alternatively be configured and used as a BSC interface.
B5
SPI0_CLK
C5
SPI0_MISO
B6
SPI0_SISO
E6
SPI0_CS
O SPI clock
I
SPI data master in
O SPI data master out
O SPI slave select
UART Interface
A7
UART0_CTS
I
UART clear-to-send
B7
UART0_RTS
O UART request-to-send
C7
UART0_RXD
I
UART serial input
B8
UART0_TXD
O UART serial output
Voltage Regulators (Integrated)
B12
SR_VDDBAT5V
I
VBAT.
A11
SR_VLX
O CBUCK switching regulator output
C12
LDO_VDD1P5
I
LNLDO input
D12
LDO_VDDBAT5V
I
LDO VBAT
N6
WRF_XTAL_VDD1P35 I
XTAL LDO input (1.35V)
M6
WRF_XTAL_VDD1P2 O XTAL LDO output (1.2V)
D11
VOUT_LNLDO
O Terminate with 2.2 µF capacitor to GND
B11
VOUT_CLDO
O Output of core LDO
E12
VOUT_3P3
O LDO 3.3V output
B10
VOUT_CLDO_SENSE O Voltage sense pin for core LDO
C11
VOUT_HSICLDO
O Output of HSIC LDO
Broadcom^®
March 12, 2016 • 43903-DS102-R
BROADCOM CONFIDENTIAL
Page 48