BCM43903 Datasheet, PDF (34/87 Pages) Cypress Semiconductor – WICED™ IEEE 802.11 b/g/n SoC with an Embedded Applications Processor

BCM43903 Preliminary Data Sheet
IEEE 802.11n MAC
PSM
The programmable state machine (PSM) is a microcoded engine that provides most of the low-level control to
the hardware in order to implement the IEEE 802.11 specification. It is a microcontroller that is highly optimized
for flow-control operations, which are predominant in implementations of communication protocols. The
instruction set and fundamental operations are simple and general, allowing algorithms to be optimized very late
in the design process. It also allows for changes to the algorithms to track evolving IEEE 802.11 specifications.
The PSM fetches instructions from microcode memory. It uses the shared memory to obtain operands for
instructions, as a data store, and to exchange data between both the host and the MAC data pipeline (via the
SHM bus). The PSM also uses a scratch-pad memory (similar to a register bank) to store frequently accessed
and temporary variables.
The PSM exercises fine-grained control over the hardware engines by programming internal hardware registers
(IHR). These IHRs are colocated with the hardware functions they control and are accessed by the PSM via the
IHR bus.
The PSM fetches instructions from the microcode memory using an address determined by the program
counter, instruction literal, or a program stack. For ALU operations, the operands are obtained from shared
memory, scratch-pad memory, IHRs, or instruction literals, and the results are written into the shared memory,
scratch-pad memory, or IHRs.
There are two basic branch instructions: conditional branches and ALU-based branches. To better support the
many decision points in the IEEE 802.11 algorithms, branches can depend on either readily available signals
from the hardware modules (branch condition signals are available to the PSM without polling the IHRs) or on
the results of ALU operations.
WEP
The wired equivalent privacy (WEP) engine encapsulates all the hardware accelerators to perform encryption
and decryption as well as MIC computation and verification. The accelerators implement the following cipher
algorithms: legacy WEP, WPA TKIP, WPA2 AES-CCMP.
The PSM determines, based on the frame type and association information, the appropriate cipher algorithm to
use. It supplies the keys to the hardware engines from an on-chip key table. The WEP interfaces with the
transmit engine (TXE) to encrypt and compute the MIC on transmit frames and the receive engine (RXE) to
decrypt and verify the MIC on receive frames.
Broadcom^®
March 12, 2016 • 43903-DS102-R
BROADCOM CONFIDENTIAL
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