BCM43903 Datasheet, PDF (26/87 Pages) Cypress Semiconductor – WICED™ IEEE 802.11 b/g/n SoC with an Embedded Applications Processor

BCM43903 Preliminary Data Sheet
Cryptography Core
Cryptography Core
This core provides general purpose data movement between memories, which may be either on the device,
attached directly to the device, or accessed through a host interface. The transmit/pull engine reads data from
the source memory and passes it immediately to the paired receive/push engine that proceeds to write it to the
destination memory. Multiple masters may program the individual channels, and multiple interrupts are provided
so that interrupts for different channels can be routed separately to different masters.
The cryptography block provides a hardware accelerator for enciphering and deciphering data that has
undergone processing using standards-based encryption algorithms. The cryptography block includes the
following primary features:
• Encryption and hash engines that support single pass AUTH-ENC or ENC-AUTH processing.
• A scalable AES module that supports CBC, ECB, CTR, CFB, OFB, and XTS encryption with 128-, 192-,
and 256-bit key sizes.
• A scalable DES module that supports DES and 3DES in ECB and CBC modes.
• An RC4 stream cipher module that supports state initialization, state update, and key-stream generation.
• MD5, SHA1, SHA224, and SHA256 engines that support pure hash or HMAC operations.
• A built-in 512-byte key cache for locally protected key storage.
OTP memory is used to store authentication keys.
Broadcom^®
March 12, 2016 • 43903-DS102-R
BROADCOM CONFIDENTIAL
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