BCM43903 Datasheet, PDF (18/87 Pages) Cypress Semiconductor – WICED™ IEEE 802.11 b/g/n SoC with an Embedded Applications Processor

BCM43903 Preliminary Data Sheet
Power Management
Mode
Active
Doze
Deep-sleep
Power-down
Table 1: BCM43903 Power Modes
Description
All WLAN blocks in the BCM43903 are powered up and fully functional with active carrier
sensing and frame transmission and receiving.
All required regulators are enabled and put in the most efficient mode based on the load
current. Clock speeds are dynamically adjusted by the PMU sequencer.
The radio, analog domains, and most of the linear regulators are powered down.
The rest of the BCM43903 remains powered up in an idle state. All main clocks (PLL, crystal
oscillator, or TCXO) are shut down to minimize active power consumption. The 32.768 kHz
LPO clock is available only for the PMU sequencer. This condition is necessary to allow the
PMU sequencer to wake up the chip and transition to Active mode. In Doze mode, the primary
power consumed is due to leakage current.
Most of the chip, including both analog and digital domains and most of the regulators, is
powered off.
Logic states in the digital core are saved and preserved in a retention memory in the Always-
On domain before the digital core is powered off. Upon a wake-up event triggered by the PMU
timers or an external interrupt, logic states in the digital core are restored to their pre-deep-
sleep settings to avoid lengthy HW reinitialization.
The BCM43903 is effectively powered off by shutting down all internal regulators.
The chip is brought out of this mode by external logic re-enabling the internal regulators.
Broadcom^®
March 12, 2016 • 43903-DS102-R
BROADCOM CONFIDENTIAL
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