BCM43903 Datasheet, PDF (17/87 Pages) Cypress Semiconductor – WICED™ IEEE 802.11 b/g/n SoC with an Embedded Applications Processor

BCM43903 Preliminary Data Sheet
Power Management
Figure 4: Typical Power Topology (Page 2 of 2)
BCM43903 2.5V and 3.3V
VBAT
LDO3P3
3.3V
450 to
800 mA
WLRF PA
WLRF Pad
VDDIO_RF
WL OTP 3.3V
2.5V Cap-less
LNLDO
2.5V Cap-less
LNLDO
2.5V Cap-less
LNLDO
2.5V
2.5V
VCOLDO2P5
Inside WL Radio
WL RF RX, TX, NMOS, Mini-PMU LDOs
WL RF VCO
WL RF CP
Supply ball
Ground ball
Supply bump/pad
Ground bump/pad
External to chip
Power
switch
No power switch
No dedicated power switch, but internal power-
down modes and block-specific power switches
Power Management
The BCM43903 has been designed with the stringent power consumption requirements of mobile devices in
mind. All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell
libraries were chosen to reduce leakage current and supply voltages. Additionally, the BCM43903 includes an
advanced Power Management Unit (PMU) sequencer. The PMU sequencer provides significant power savings
by putting the BCM43903 into various power management states appropriate to the environment and activities
that are being performed. The power management unit enables and disables internal regulators, switches, and
other blocks based on a computation of the required resources and a table that describes the relationship
between resources and the time needed to enable and disable them. Power-up sequences are fully
programmable. Configurable, free-running counters (running at a 32.768 kHz LPO clock) in the PMU sequencer
are used to turn on and turn off individual regulators and power switches. Clock speeds are dynamically
changed (or gated altogether) as a function of the mode. Slower clock speeds are used whenever possible.
Table 1 provides descriptions for the BCM43903 power modes.
Broadcom^®
March 12, 2016 • 43903-DS102-R
BROADCOM CONFIDENTIAL
Page 16