CM6533-N Datasheet, PDF (44/60 Pages) C-Media Electronics – USB 2.0 Full-Speed compliant

CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
6.10 GPIO
6.10.1 GPO Data Register
Address Offset: C0-C1h
Bits R/W
15:0 R/W
Bit Mnemonic
GPO_0_reg
GPO_1_reg
Description
GPO data register which represents
6.10.2 GPI Data Register
Address Offset: C2-C3h
Bits R/W
Bit Mnemonic
Description
15:0 R
GPI data register which represents
Default
16’h0
(POR)
Default
16’h0
(POR)
6.10.3 GPIO Direction Control Register
Address Offset: C4-C5h
Bits R/W
15:0 R/W
Bit Mnemonic
GPOE_0
GPOE_1
Description
GPIO output enable register which
represents for pin XGPIO[15:0]
1: the corresponding pins are used as
output
0: the corresponding pins are used as input
6.10.4 GPIO Interrupt Enable Mask Register
Address Offset: C6-C7h
Bits R/W
15:0 R/W
Bit Mnemonic
GPI_EN
Description
GPIO_E, GPIO interrupt enable mask which
represents for pins, XGPIO[15:0]
1: enable, 0: disable
6.10.5 GPIO Debouncing Register
Address Offset: C8-C9h
Default Value: 0000h (MSB -> LSB)
Bits R/W
15:0 R/W
Bit Mnemonic
GPI_Deb
Description
Enable the clock scale of mini-second (32
ms) for de-bouncing, default 1
1: enable, 0: disable
Default
16’h0
(POR)
Default
16’h0
(POR)
Default
16’h0
(POR)
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Rev.1.6
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