CM6533-N Datasheet, PDF (39/60 Pages) C-Media Electronics – USB 2.0 Full-Speed compliant

CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
Others: Reserved
0
R
busy
The 2-wire serial bus status, 0: idle, 1: busy
0b
(POR)
**Note: When I2C issue interrupt to MCU, MCU needs to read the data numbers that threshold data count specified.
And waits another interrupt until the total data transfer completed.
6.8.14 I2C Slave Memory Address Pointer(MAP) Register
Address: 36h
Bits R/W
7:0 R/W
Bit Mnemonic
MCU_MAP
Description
The memory addresses of the read or write transactions
from MCU. Address 0 is reserved for initiated
transaction.
Default
00h
(POR)
6.8.15 I2C Slave Status Register
Address: 37h
Bits R/W
7 R/W
6 R/W
5:4 R/W
Bit Mnemonic
Sync_en
Int_polarity
Slave_addr
Description
Synchronization Enable
1: enable (the synchronization selection bit will decide
the method adopted).
0: disable (MCU and ARC should guarantee no data lost
themselves).
The polarity control of pin INT_OUT (initiated
transaction interrupt),
0: high active, 1: low active
Slave Device Address
00: select 0001000 (10h) as slave address
01: select 0001001 (12h) as slave address
10: select 0001010 (14h) as slave address
11: select 0001011 (16h) as slave address
Synchronization Method Selection
1: Data synchronization. When this bit is one, if the
current transaction has not been serviced by ARC, the
clock line of the 2-wire serial bus will be pulled low.
Under this situation, the MCU cannot start a new
transaction or continue the current read transaction
until the clock line goes back to high.
3 R/W
Sync_sel
0: Ready pin synchronization. If the MCU cannot support
open drain 2-wire serial bus, this bit should be set to
zero. Under this situation, the MCU cannot start a new
transaction or continue the current read transaction
until the pin XSLAVE_RDY goes high to signal that the
driver has serviced the current transaction. Driver
should use “driver acknowledge” to signal the processing
of the current transaction is completed.
Interrupt Mask
2 R/W
Int_mask
0: interrupt will happen at a read/write transaction
received or a driver initiated transaction failed
1: interrupt will not happen
Driver initiated transaction
Write 1 to start Driver initiated transaction. This bit is
1
R/W
Dri_init_tran
cleared automatically, after ARC initiated transaction
starts. The ARC initiated transaction should be issued
only when the 2-wire slave serial bus is idle. Otherwise,
it will be ignored. The ARC initiated transaction will
Default
1b
(POR)
0b
(POR)
01b
(POR)
1b
(POR)
0b
(POR)
0b
(POR)
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Rev.1.6
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